Logic Design Verification Using Redundant Representation Randomness
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Solution Overview
Problem
Current methods for verifying logic designs with redundant representations are inefficient and fail to ensure functional correctness across different implementations, leading to potential system failures due to improper manipulation of redundant numeric representations.
Innovation Solution
A computer-implemented method that involves obtaining a logic component with redundant outputs, computing both redundant and non-redundant representations, injecting a randomness factor, constraining the representations, and simulating them with downstream logic to verify the component's functionality independently of its implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional simulation or formal verification is used, then verification can be performed, but it fails to ensure functional correctness across different implementations due to polymorphism in redundant representations
Solution Approach 1:
The patent changes the verification approach from checking specific redundant representation values to verifying that the reduction function produces consistent non-redundant results across multiple redundant representations. This parameter change in verification strategy enables implementation independence while maintaining functional correctness.
Solution Approach 2:
The verification method is designed to be universal across different implementations by checking that the reduction function V(x)=R({V1, V2, ..., Vm}) produces consistent results regardless of which redundant representation is used. This universal verification approach ensures functional correctness across all implementation variations.
2Reliability
If detailed design analysis is performed on library components, then functional correctness can be ensured, but computational and time costs become exorbitant for large electronic systems
Solution Approach 1:
The patent extracts the essential verification requirement from detailed design analysis by focusing only on the reduction function's ability to produce consistent non-redundant results. This extraction eliminates unnecessary computational overhead while preserving functional correctness verification.
Solution Approach 2:
The verification method performs preliminary checking of the reduction function's consistency across redundant representations before full system integration. This preliminary action ensures functional correctness early in the design process, avoiding costly re-verification later.
3Speed
If redundant representations are used to enhance performance, then arithmetic operations can be accelerated, but polymorphism is introduced that causes output vectors to change with implementation
Solution Approach 1:
The patent introduces feedback verification that checks whether the reduction function produces consistent non-redundant outputs across different redundant representations. This feedback mechanism ensures output consistency while allowing performance-optimized redundant representations to be used.
Data Source
AI summary
Computer-implemented techniques are disclosed for verifying functional independence of logic designs that make use of redundant representations. Initially, the design of a logic component is obtained. Two representations of the component are computed, one in redundant form and another in non-redundant form. A randomness factor based on a time-varying value is injected into the second representation. The value from the second form is then constrained to the context of the logic component within a digital system. It is then possible to analyze the component using the first deterministic representation and the constrained second representation. This analysis allows verification of the component with downstream logic.