Logic Device Defect Segregation via Automated Test Patterns
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Solution Overview
Problem
Traditional semiconductor manufacturing techniques result in defects in logic devices like SIMDs due to inherent impurities, which can render devices inoperable, necessitating efficient defect testing and compensation methods to ensure performance and yield.
Innovation Solution
An apparatus and method for testing logic devices using automated testing mechanisms that output test patterns and include a fusing mechanism to compensate for defects, allowing for the identification and segregation of defective components, enabling continued operation at a reduced quality level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional semiconductor manufacturing techniques are used, then production volume is maintained, but defect occurrence increases due to inherent impurities
Solution Approach 1:
The patent implements preliminary action by performing automated testing and defect identification on logic devices before they are fully integrated into final products. The system tests devices at an intermediate stage, identifies defects early, and segregates defective units before they reach production completion, thereby maintaining production volume while improving reliability through early defect detection.
Solution Approach 2:
The patent introduces an intermediary testing and classification system between manufacturing and final product integration. This intermediary mechanism includes automated testing equipment and defect analysis systems that act as a mediator to evaluate logic devices, determine their operational status, and route them to appropriate destinations (functional devices to production, defective devices to segregation), thus resolving the contradiction between maintaining production volume and reducing defect occurrence.
2Measurement precision
If automated testing mechanisms are implemented, then defect identification accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the testing system into modular components: automated testing mechanisms, defect analysis systems, and segregation mechanisms. Each module performs a specific function independently, which improves defect identification accuracy while managing complexity through modular design. The testing process itself is segmented into multiple stages (initial testing, detailed analysis, classification) that can be implemented incrementally.
Solution Approach 2:
The automated testing mechanisms are designed to self-configure and self-diagnose defects without requiring complex external intervention. The system automatically generates test patterns, analyzes results, and determines device status independently, reducing the operational complexity despite the advanced capabilities of the testing equipment.
3Reliability
If defective devices are segregated, then product reliability is improved, but manufacturing efficiency decreases
Solution Approach 1:
The patent performs defect segregation as a preliminary action before final product assembly. By identifying and segregating defective logic devices early in the manufacturing process, the system prevents defective units from progressing to later stages, thereby improving final product reliability. The segregation occurs at an optimal point in the manufacturing flow where defect detection is most efficient, minimizing the impact on overall manufacturing efficiency.
Solution Approach 2:
The system implements feedback mechanisms where test results from automated testing are immediately fed back to control the segregation process. This closed-loop feedback enables real-time decision-making about which devices to segregate, optimizing the balance between reliability improvement and manufacturing efficiency by avoiding unnecessary segregation of functional devices while ensuring defective ones are captured.
Data Source
AI summary
Provided is an apparatus configured for testing a logic device. The apparatus includes a testing mechanism configured to output test patterns representative of logical structures within the logic device and a testable logic device having (i) input ports coupled to output ports of the automated testing mechanism and (ii) output ports coupled to input ports of the automated testing mechanism. The apparatus also includes a fusing mechanism configured to compensate for defects within the logic device responsive to a segregation of the type of defects identified.