Logic Device Isolation in Embedded Storage Process
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Solution Overview
Problem
The challenge is to maintain consistent device characteristics in logic devices formed during the embedded storage process, as existing methods do not ensure the same performance as those formed in a standard logic process, particularly in the isolation process of narrow channel devices.
Innovation Solution
The method involves generating a floating gate oxide layer and polysilicon layer on a silicon substrate, followed by shallow trench isolation lithography, vertical dry etching to remove specific layers, acid etching, lateral SiN pull-back, silicon oxide filling, and chemical mechanical polishing to form logic device isolation, ensuring consistent characteristics with standard logic processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common storage process isolation method is used, then the isolation structure is formed, but the logic device characteristics differ from those in standard logic processes
Solution Approach 1:
The isolation process is divided into multiple sequential steps: forming pad oxide and nitride layers, performing shallow trench isolation lithography and etching, conducting lateral SiN pull-back, and executing silicon oxide filling with CMP. This segmentation allows each step to be optimized independently to achieve both characteristic consistency and process compatibility
Solution Approach 2:
The pad oxide and pad nitride layers are formed in advance before the shallow trench isolation etching. These preliminary layers serve as etch stop layers that prevent etching into the floating gate oxide, ensuring device characteristic consistency while enabling subsequent isolation processing
2Manufacturing precision
If shallow trench isolation etching is performed without etch stop layers, then the isolation trench is formed, but the floating gate oxide layer is damaged
Solution Approach 1:
The pad oxide and pad nitride layers are deposited beforehand to cushion and protect the floating gate oxide layer during the shallow trench isolation etching process. These layers absorb the etching action and prevent direct contact between the etch plasma and the floating gate oxide, eliminating damage while enabling precise trench formation
Solution Approach 2:
The pad oxide and pad nitride layers act as intermediary protective layers between the etching process and the floating gate oxide. They serve as sacrificial etch stop layers that can be selectively removed later via lateral SiN pull-back, thereby protecting the critical floating gate oxide during isolation formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures that logic devices in embedded storage processes maintain the same characteristics as those in logic processes, enhancing device performance and consistency.
Implementation Method 1
perform vertical dry etching to remove the pad silicon nitride and floating gate polysilicon layer in a shallow trench isolation area
Implementation Method 2
perform chemical mechanical polishing to form logic device isolation
Data Source
AI summary
A method for manufacturing logic device isolation in an embedded storage process, removing the pad silicon nitride and floating gate polysilicon layer in a shallow trench isolation area and retaining the floating gate oxide layer; depositing acid etching silicon nitride; removing the acid etching silicon nitride at the bottom of the shallow trench isolation and a portion of the silicon substrate adjacent to and under the shallow trench isolation, to form a trench and retain the acid etching silicon nitride on a side of the floating gate polysilicon layer close to the shallow trench isolation; remove the acid etching silicon nitride on the side of the floating gate polysilicon layer close to the shallow trench isolation.