Programmable Logic Device Blocks Memory Buffer Reset
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Solution Overview
Problem
Computing systems often lose error data during system resets, which hampers diagnostic evaluation as error logs are cleared, especially in memory buffer devices that experience errors prompting a system-wide reset.
Innovation Solution
A programmable logic device is configured to block the reset of memory buffer devices and other error-generating components during a system reset, allowing error data to be retrieved and stored in nonvolatile memory after the reset, ensuring its preservation for diagnostic purposes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a system-wide reset is performed to clear errors, then system reliability is improved, but error data is lost making diagnosis difficult
Solution Approach 1:
The patent extracts error data from volatile memory before the system reset occurs by transferring it to non-volatile memory or a dedicated error logging component. This extraction ensures that error information is preserved separately from the main system memory that undergoes reset, resolving the contradiction between system reliability improvement through reset and error data preservation for diagnosis.
Solution Approach 2:
The patent implements preliminary action by capturing and storing error data in non-volatile memory before the system reset is executed. This advance preservation of error information ensures that diagnostic data remains intact even after the reset clears volatile memory, allowing both system recovery and error analysis to proceed effectively.
2Stability of the object's composition
If memory buffer devices are reset during system reset, then system stability is improved, but error logs are cleared impacting diagnostic evaluation
Solution Approach 1:
The patent extracts error logs from the memory buffer device's volatile memory before reset by transferring them to non-volatile storage or a dedicated error logging component. This extraction allows the memory buffer to be reset for system stability while preserving the error log data for subsequent diagnostic evaluation.
Solution Approach 2:
The patent introduces an intermediary error logging component or non-volatile memory that acts as a buffer between the volatile memory buffer device and the diagnostic system. This intermediary preserves error log data during the reset process, enabling both system stability restoration and diagnostic evaluation without direct conflict.
3Reliability
If all components are reset during system reset, then error conditions are cleared, but diagnostic information is lost
Solution Approach 1:
The patent extracts diagnostic information from volatile memory components before system reset by transferring it to non-volatile memory or a dedicated error logging component. This extraction enables complete system reset for error clearance while preserving diagnostic information for later analysis.
Solution Approach 2:
The patent implements preliminary action by capturing and storing diagnostic information in non-volatile storage before the system reset is executed. This advance preservation ensures that all diagnostic data remains intact even after the reset clears all volatile memory, allowing both error clearance and diagnostic evaluation to proceed effectively.
Data Source
AI summary
Various techniques for managing a system reset of a computing system to maintain error data are described herein. In one example, a computing system configured for managing a system reset to maintain error data comprises a memory buffer device to receive a transaction from a system processor and to notify the system processor of an error in performing the transaction to volatile memory. In some examples, the system processor is configured to initiate a system reset of the computing system in response to the error, the system reset comprising a reset of the memory buffer device. Furthermore, the computing system includes an integrated circuit to block the reset of the memory buffer device to maintain error data in the volatile memory.