Logic Diagram Error Point Estimation Without Fault Dictionary
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing supervisory control systems face challenges in efficiently estimating error points in logic diagrams due to the need for extensive fault simulations and database preparation, leading to high calculation times and data volume issues, especially as circuit scales increase.
Innovation Solution
A device and method for estimating error points in logic diagrams that includes a logic diagram storage, test table storage, signal line correctness/incorrectness determining unit, signal line correctness/incorrectness result summarizing unit, and error signal line estimating unit, which determines and displays the correctness or incorrectness of signal lines based on test results without requiring a fault dictionary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fault simulation and fault dictionary generation are performed to estimate error points, then error point estimation accuracy is improved, but calculation time and data volume increase significantly
Solution Approach 1:
The patent extracts only the essential test information needed for error point estimation from the logic diagram, creating a simplified test table that contains input-output relationships without requiring comprehensive fault simulation. This extraction approach maintains estimation accuracy while eliminating the time-consuming fault dictionary generation process.
Solution Approach 2:
The patent performs preliminary analysis of the logic diagram to identify testable signal lines and create a test table before actual error point estimation. This preliminary action prepares the necessary test data structure in advance, allowing rapid error point estimation without repeated fault simulations during the actual debugging process.
2Reliability
If fault simulation and fault dictionary are used for error point estimation, then error detection capability is improved, but data volume and storage requirements increase
Solution Approach 1:
The patent extracts only the necessary test cases and signal line information from the logic diagram into a compact test table format. This extraction eliminates the need to store large fault dictionaries while maintaining the capability to detect errors effectively through targeted testing of identified signal lines.
3Ease of operation
If manual tracking of control logic is performed to specify error points, then error point identification is possible, but time consumption increases significantly for complicated control logic
Solution Approach 1:
The patent enables the system to automatically identify error points by evaluating test results against the test table and automatically tracking signal lines through the logic diagram. This self-service approach eliminates the need for manual error point specification, allowing the system to autonomously identify errors even in complicated control logic without significant time consumption.
4Measurement precision
If comprehensive test coverage is performed on all signal lines, then error detection accuracy is improved, but test complexity and time requirements increase
Solution Approach 1:
The patent extracts and focuses testing only on signal lines that can be evaluated through the test table approach, rather than requiring comprehensive testing of all signal lines in the logic diagram. This selective extraction maintains error detection accuracy for critical paths while reducing overall test complexity.
Data Source
AI summary
A technique capable of estimating an error point in a logic diagram appropriately. A logic diagram display device includes: a signal line correctness/incorrectness determining unit that determines for each test whether each signal line in the logic diagram is correct or incorrect based on a signal line status value of each signal line and a test table; and a signal line correctness/incorrectness result summarizing unit that calculates a correctness/incorrectness result summarized value of each signal line based on a result of determination about the correctness or incorrectness of each signal line. The logic diagram display device further includes: an error signal line estimating unit that estimates an error in each signal line based on the correctness/incorrectness result summarized value of each signal line; and a display that displays each signal line in the logic diagram in a display style responsive to the error in each signal line.