Stacked DRAM Repair Using Logic-Die ECC and TSV Fault Isolation
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Solution Overview
Problem
Conventional memory devices face limitations in increasing data bandwidth, leading to performance issues due to defective memory cells, especially as capacity grows, making it difficult to effectively repair these devices.
Innovation Solution
A high-capacity, high-bandwidth memory device design that includes stacked DRAM dice connected by through silicon vias, with a logic die that performs error checking and correction, and a block repair system to replace defective memory cells with redundant rows or columns, optimizing data transfer and repair processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory capacity is increased to achieve higher memory bandwidth, then data bandwidth is improved, but the likelihood of defective memory cells increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring redundant memory cells and repair logic circuits during manufacturing, before defects occur. The repair mechanism is prepared in advance with replacement rows and columns of memory cells that can be activated through repair masks to substitute defective cells, enabling immediate correction without system downtime.
Solution Approach 2:
The patent employs parameter changes by dynamically altering the operational parameters of the memory device through repair masks that modify address decoding and data routing. When defects are detected, the system changes the active memory cell addresses and data paths to bypass defective cells and utilize redundant cells, effectively changing the operational parameters of the memory array.
2Reliability
If conventional repair methods substitute redundant rows or columns for defective memory cells, then defective cells are repaired, but repair complexity increases with vastly increased memory capacity
Solution Approach 1:
The patent applies segmentation by organizing the memory device into distinct segments including multiple memory arrays, separate redundant memory cells, and dedicated repair logic circuits. The memory device is divided into replaceable rows and columns with associated repair masks, allowing localized repair operations that do not require complex system-wide modifications, thereby managing complexity through modular segmentation.
Solution Approach 2:
The patent introduces intermediary elements including repair masks and address decoding logic that act as mediators between the control logic and memory cells. These intermediaries simplify the repair process by providing a standardized interface for defect management, where repair masks serve as intermediary layers that redirect access from defective cells to redundant cells without requiring complex direct manipulation of memory cell connections.
Data Source
AI summary
Memory systems, systems and methods are described that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias.