Thick Logic Die PoP Structure With Copper-Cored Solder Ball Gap Control
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Solution Overview
Problem
Current semiconductor package technologies face challenges in enhancing thermal dissipation and interconnect efficiency, particularly in Package-on-Package (PoP) structures used in high-end mobile devices, which require improved performance and reliability.
Innovation Solution
A thermally enhanced semiconductor package design featuring a thick logic die mounted on a bottom substrate with copper cored solder balls and sealing resin to create a gap between substrates, allowing for efficient electrical connection and thermal management, along with a flip-chip configuration and underfill resin for enhanced reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a thick logic die is used in PoP structure, then thermal dissipation efficiency is improved, but device height increases
Solution Approach 1:
The patent implements Package-on-Package (PoP) structure where memory packages are stacked vertically on top of the logic die, creating a nested configuration. This allows the thick logic die to maintain its thermal dissipation advantages while the overall device footprint is minimized through vertical integration, effectively managing the height parameter through spatial reorganization.
Solution Approach 2:
The patent transitions from horizontal layout to vertical stacking by implementing PoP architecture, moving the solution into the vertical dimension. This allows thermal management to be optimized independently in the horizontal plane while the vertical height is managed through compact stacking arrangements and optimized substrate thickness.
2Reliability
If copper cored solder balls with optimized aspect ratio are used, then interconnect efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the aspect ratio of copper cored solder balls within a specific range (1.05-1.3) to balance interconnect efficiency with manufacturability. By controlling the height-to-diameter ratio within this optimized range, the patent achieves improved thermal and electrical conductivity while maintaining compatibility with existing solder ball placement processes, avoiding excessive precision requirements.
Solution Approach 2:
The patent uses copper cored solder balls specifically at strategic locations around the logic die perimeter, providing enhanced local thermal and electrical conductivity where it is most needed for heat dissipation and signal integrity, while maintaining standard solder ball specifications in other areas, thus balancing performance improvement with manufacturing feasibility.
3Temperature
If gap height between substrates is optimized, then thermal dissipation is improved, but structural stability decreases
Solution Approach 1:
The patent optimizes the gap height between substrates within a specific range (0.1-0.3 times the logic die thickness) to maximize thermal dissipation efficiency through convection and radiation pathways, while simultaneously maintaining structural stability by ensuring the gap is not so large as to compromise mechanical support and alignment of the stacked packages.
Solution Approach 2:
The patent introduces underfill resin as an intermediary material between the logic die and substrates, which fills the gap space to provide mechanical support and stability while allowing sufficient thermal pathways to remain open for heat dissipation. The underfill acts as a mediator that simultaneously addresses both structural stability and thermal management requirements.
4Reliability
If sealing resin coverage is increased, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies sealing resin with coverage optimized to cover critical areas around the logic die and interconnect structures, providing sufficient protection and sealing reliability for the most vulnerable regions, while avoiding excessive coverage that would unnecessarily increase manufacturing complexity and material usage. The sealing resin is applied to achieve functional adequacy rather than complete coverage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves thermal dissipation and interconnect efficiency, enhancing the performance and reliability of semiconductor packages by optimizing the gap height and aspect ratio of copper cored solder balls, and sealing resin coverage, thereby addressing the limitations of existing PoP structures.
Implementation Method 1
A plurality of copper cored solder balls disposed between the bottom substrate and the top substrate around the logic die
Implementation Method 2
a sealing resin filling in the gap between the bottom substrate and the top substrate and sealing the logic die and the plurality of copper cored solder balls in the gap
Implementation Method 3
underfill resin is disposed in a space between the logic die and the top surface of the bottom substrate, and wherein the conductive elements are surrounded by the underfill resin
Data Source
AI summary
A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate. The logic die has a thickness of 125-350 micrometers. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills into the gap between the bottom substrate and the top substrate and sealing the logic die and the plurality of copper cored solder balls in the gap.