Configurable Logic Die Interface for Mirrored HBM Pin Alignment
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Solution Overview
Problem
In multi-chip packages, the mismatch between the order of High Bandwidth Memory (HBM) I/O pins on the logic die and the on-package memory tile leads to routing complexity and reduced yield due to die splitting techniques.
Innovation Solution
A configurable physical interface on the logic die allows for mirroring of the HBM interface I/O pins, enabling alignment with the on-package memory tile's I/O pins, thereby simplifying routing and maintaining yield improvements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If die splitting technique is used to increase yield, then productivity is improved, but device complexity increases due to routing mismatch between logic die and memory tile
Solution Approach 1:
The patent implements a configurable physical interface that can dynamically change its pin ordering configuration. The interface is designed to support multiple pin orderings and can be configured at test time or operation time to match different memory tile orientations, allowing the system to adapt to various routing scenarios without increasing complexity
Solution Approach 2:
The patent changes the parameter of pin ordering configuration from fixed to variable. By allowing the physical interface to be configured with different pin orderings (e.g., mirrored or non-mirrored), the system can optimize routing for different die splitting scenarios, thereby reducing routing complexity while maintaining yield improvement benefits
2Device complexity
If HBM interface I/O pins are fixed in order on logic die, then device complexity is reduced, but manufacturing precision decreases due to mismatch with memory tile I/O pins
Solution Approach 1:
The physical interface is designed with configurable pin ordering that can be adjusted based on the specific memory tile orientation and routing requirements. This dynamic configuration capability allows the interface to maintain proper connectivity alignment without requiring complex fixed designs
Solution Approach 2:
The patent implements configuration mechanisms (such as pin straps or fuses) that are set during manufacturing or testing to pre-establish the correct pin ordering match between the logic die and memory tile. This preliminary configuration ensures proper connectivity alignment is achieved before the product reaches the customer
Data Source
AI summary
A multi-chip device having a configurable physical interface in a logic die to on-package memory is provided. The configurable physical interface to allow a connection from a signal on the memory interface to be selected based on whether the logic die is mirrored or non-mirrored.