Thick Logic Die Package Structure for PoP Thermal Dissipation
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Solution Overview
Problem
Current semiconductor packages face challenges in thermal dissipation and interconnect efficiency, particularly in Package-on-Package (PoP) structures used in high-end mobile devices, where the thickness of logic dies and the number of interconnects are limited, affecting performance and reliability.
Innovation Solution
A semiconductor package design featuring a thick logic die mounted on a bottom substrate in a flip-chip fashion, with copper cored solder balls and a sealing resin to enhance thermal dissipation and electrical connectivity, along with a memory package stacked on top, utilizing a LPDDR DRAM package for increased performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the logic die thickness is increased to improve thermal dissipation, then thermal performance is improved, but device height and packaging complexity increase
Solution Approach 1:
The patent transitions from planar interconnects to three-dimensional vertical interconnects by stacking multiple logic dies and memory dies in a PoP configuration. This dimensional change allows thermal management to occur through the vertical thickness of the stacked structure, improving heat dissipation while maintaining a compact footprint.
Solution Approach 2:
The patent implements a nested structure where memory dies are stacked atop logic dies, and the entire stack is encapsulated within a package substrate. This nesting approach allows multiple functional layers to be integrated vertically, improving thermal pathways while managing overall device complexity through hierarchical organization.
2Reliability
If copper cored solder balls are used to enhance electrical connectivity, then interconnect efficiency is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent employs copper cored solder balls as a composite interconnect material, where a copper core provides superior electrical conductivity and thermal conductivity, while the outer solder layer provides reliable bonding to substrates and components. This composite structure optimizes both electrical connectivity and manufacturability by combining the advantages of different materials.
3Productivity
If component density is increased in PoP structures, then device performance is improved, but thermal management difficulty increases
Solution Approach 1:
The patent distributes components across multiple vertical layers in a stacked PoP configuration, transforming the thermal management challenge from a two-dimensional plane to a three-dimensional volume. This allows heat to dissipate through multiple pathways including the thickness direction, improving thermal management despite increased component density.
Solution Approach 2:
The patent segments the integrated circuit into multiple separate dies (logic dies and memory dies) that are stacked vertically. Each die can be independently tested and optimized, and the segmentation creates distinct thermal zones that can be managed separately, improving overall thermal management while achieving high component density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves thermal performance and interconnect efficiency by increasing the logic die thickness and using copper cored solder balls for enhanced electrical connectivity, while allowing for higher component density and reliability in PoP structures.
Implementation Method 1
A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die
Implementation Method 2
A sealing resin fills in the gap between the bottom substrate and the top substrate and seals the logic die and the plurality of copper cored solder balls in the gap
Data Source
AI summary
A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate in a flip-chip fashion. The logic die has a thickness of 125-350 micrometers. The logic die comprises an active front side, a passive rear side, and an input/output pad provided on the active front side. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and seals the logic die and the plurality of copper cored solder balls in the gap.