Logic Die TSV Interface for Low-Latency Memory Stacks
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Solution Overview
Problem
Existing semiconductor devices with through silicon vias (TSVs) experience latency during signal transmission and reception due to the interface structure between memory controllers and core dies, particularly in high-bandwidth memory (HBM) systems.
Innovation Solution
A semiconductor device with a logic die that includes a memory controller, interface circuit, and TSVs, which converts voltage and synchronizes signals between different voltage and clock domains using TSV macros to facilitate direct interfacing between the memory controller and core dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interposer is used to provide the interface between memory controller and core dies, then the interface functionality is achieved, but signal transmission latency increases
Solution Approach 1:
The patent extracts the interface circuit functionality from a separate interposer structure and integrates it directly into the logic die. The TSV circuit blocks are positioned within the logic die's TSV region, eliminating the need for an external interposer and reducing signal transmission latency while maintaining interface functionality.
Solution Approach 2:
The patent merges the memory controller, interface circuit, and TSV circuit blocks into a single logic die. This integration combines previously separate components (controller and interface) into one unified structure, enabling direct communication with core dies without requiring an interposer, thereby reducing latency.
2Adaptability or versatility
If voltage level conversion is implemented between different voltage domains, then compatibility between memory controller and core dies is achieved, but circuit complexity increases
Solution Approach 1:
The patent implements voltage level conversion locally at the TSV circuit blocks that are directly connected to the TSVs. Each TSV circuit block performs voltage conversion for its specific connection point, rather than requiring a centralized complex voltage conversion system. This localized approach achieves voltage domain compatibility while minimizing overall circuit complexity.
3Reliability
If signal synchronization between different clock domains is implemented, then reliable communication between memory controller and core dies is achieved, but processing complexity increases
Solution Approach 1:
The patent implements signal synchronization locally at each TSV circuit block, which handles synchronization for its specific TSV connection. This distributed local synchronization approach achieves reliable communication between different clock domains without requiring a complex centralized synchronization system, thereby reducing processing complexity.
4Speed
If direct interfacing between memory controller and core dies is implemented, then signal transmission speed is improved, but design flexibility is reduced
Solution Approach 1:
The patent designs the logic die with a standardized TSV region and TSV circuit blocks that can accommodate multiple core dies with different voltage domains and clock domains. This universal interface design enables direct high-speed interfacing while maintaining design flexibility to support various configurations of memory devices.
Data Source
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AI summary
Provided are a logic die for supporting direct interfacing between a memory die and a memory controller via a through silicon via (TSV) and a semiconductor device including the logic die. The semiconductor device includes a logic die including a memory controller, an interface circuit, and a plurality of TSVs arranged in a TSV region. A plurality of memory dies stacked vertically on the logic die, and connected to the plurality of TSVs. The memory controller operates in a first voltage domain, and the plurality of memory dies operate in a second voltage domain. The interface circuit includes a plurality of TSV circuit blocks connected to the plurality of TSVs. Each TSV circuit block is configured to convert a voltage level of a signal, transmitted via a corresponding TSV, between a first voltage level in the first voltage domain and a second voltage level in the second voltage domain.