Logic Die TSV Repair Using Redundancy Paths and Clock Phase Shift
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Solution Overview
Problem
Existing semiconductor devices with high bandwidth memory (HBM) face increased latency and power consumption due to defects in through silicon vias (TSVs) requiring communication via an interposer, which complicates signal transmission and reception.
Innovation Solution
A logic die with a memory controller, interface circuit, and TSVs that includes TSV repair logic to reroute signals around defective TSVs, utilizing redundancy TSVs and phase shift logic to adapt synchronization clock phases, thereby facilitating efficient TSV repair operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If communication via an interposer is used for interfacing between memory controller and core dies, then signal transmission is enabled, but latency increases
Solution Approach 1:
The patent uses TSVs as direct vertical interconnects between logic die and core dies, eliminating the need for lateral signal routing through an interposer. The TSVs serve as intermediary structures that provide direct electrical pathways, reducing signal transmission distance and latency while maintaining reliable communication.
Solution Approach 2:
The patent transitions from lateral/planar signal routing through an interposer to vertical signal transmission through TSVs. By changing the dimension of signal pathways from horizontal to vertical, the patent reduces signal path length and eliminates interposer-related latency.
2Reliability
If TSV repair operation is performed using existing structures, then defect correction is possible, but device complexity increases
Solution Approach 1:
The patent incorporates redundancy TSVs and TSV repair logic during the initial device fabrication stage. These repair mechanisms are pre-configured and integrated into the device structure, allowing defect correction without adding external complexity or requiring post-manufacturing modifications.
Solution Approach 2:
The patent changes the operational parameters of TSVs by introducing redundancy configurations and repair logic that can dynamically alter signal routing paths. When defects are detected, the system changes which TSVs are active and which are used for repair, managing complexity through parameter control rather than structural additions.
Data Source
AI summary
A logic die for performing a through silicon via (TSV) repair operation and a semiconductor device including the logic die are provided. The semiconductor device includes the logic die including a memory controller and an interface circuit, a plurality of core dies stacked in a vertical direction on the logic die, each of the plurality of core dies including a memory cell array, and a plurality of through silicon vias (TSVs) configured to electrically connect the logic die to the plurality of core dies, the plurality of TSVs including a plurality of operation TSVs and at least one redundancy TSV. The interface circuit includes a plurality of TSV circuit blocks electrically connected to the plurality of TSVs, respectively, and a TSV repair logic configured to perform a repair operation on a first TSV, in which a defect occurs and a first TSV circuit block, electrically connected to the first TSV.