Digital Logic Driver Topology for Wide-Band Energy Recovery
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Solution Overview
Problem
On-chip clocking circuits experience significant power wastage and heating due to repetitive energization and de-energization, limiting their performance, and existing methods like DVFS and resonant strategies are not compatible with high-speed operations or concurrent use.
Innovation Solution
The implementation of reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies, featuring a digital logic driver with an inductor coupled in series for resonating with load capacitance to reuse electrical energy without disrupting signal paths, enabling compatibility with dynamic voltage and frequency scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If resonant strategies are used to reduce power consumption, then energy efficiency is improved, but they cannot be used concurrently at GHz speeds
Solution Approach 1:
The patent divides the clock network into multiple resonant clocking domains, each operating independently at different frequencies. This segmentation allows different parts of the system to operate at optimal speeds while maintaining energy efficiency within each domain, resolving the contradiction between power savings and high-speed operation.
Solution Approach 2:
The patent implements dynamic frequency scaling within resonant clocking domains, allowing the system to adaptively adjust operating frequencies based on workload requirements. This dynamic approach enables the system to maintain GHz speeds when necessary while exploiting resonant power savings when lower speeds suffice.
2Use of energy by moving object
If DVFS is used to save average energy, then power consumption is reduced, but energy is wasted every time an output transitions from one to zero states
Solution Approach 1:
The patent converts the harmful energy dissipation during voltage transitions into a beneficial phenomenon by exploiting resonant oscillations. The energy that would normally be wasted during transitions is instead used to excite resonant modes in the clock network, which then sustain oscillations with minimal additional energy input, effectively turning transition losses into useful energy storage.
Solution Approach 2:
The patent utilizes the phase relationships in resonant oscillations to synchronize voltage transitions across the clock network. By coordinating transitions to occur at optimal phases of the resonant cycle, the system minimizes energy loss during state changes while maintaining the average energy savings achieved through DVFS.
3Loss of energy
If resonant clocking is implemented, then energy recovery is achieved, but it interferes with signal paths and increases skew
Solution Approach 1:
The patent isolates resonant clocking operations into separate domains that are carefully bounded and controlled. By segmenting the clock network into independent resonant domains with controlled impedance interfaces, the patent prevents resonant oscillations from interfering with adjacent signal paths while maintaining energy recovery benefits within each domain.
Solution Approach 2:
The patent introduces buffer circuits and impedance matching networks as intermediaries between resonant clocking domains and the rest of the system. These intermediary elements isolate the resonant oscillations from signal paths, preventing skew and interference while allowing energy recovery to occur within the resonant domains.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and heating by reusing energy during voltage transitions, maintaining low skew and matching requirements for high-speed operations, and is compatible with DVFS, extending the frequency range of resonant clocking networks.
Implementation Method 1
an inductor coupled in series for resonating with load capacitance to reuse electrical energy
Implementation Method 2
A digital logic driver comprising a pulldown switch, an energy saving component (e.g., inductor) coupled in series with the pulldown switch
Data Source
AI summary
Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A digital logic driver comprising a pulldown switch, an energy saving component (e.g., inductor) coupled in series with the pulldown switch, and a reference supply connected in series with the energy saving component that is configured to enable the digital logic driver to resonate with a load capacitance and reuse electrical energy at the load capacitance without interfering with a signal path of the digital logic driver.