Logic Gate Driver Circuit to Cut Standby NBTI Stress
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Solution Overview
Problem
Conventional methods to address Negative Bias Temperature Instability (NBTI) in transistors, such as guard banding, gate sizing, and Vdd/Vt tuning, result in performance sacrifices, area overhead, and increased power consumption, while failing to effectively mitigate NBTI degradation in logic gate drivers during standby modes.
Innovation Solution
The proposed solution involves a logic gate driver circuit that includes a NOR gate coupled with an NMOS transistor and a control circuit with a NAND gate to turn off the operational PMOS transistor during standby mode, utilizing a sacrificial PMOS transistor to maintain the output node at a logical 1, thereby reducing NBTI degradation without significant area overhead or power increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If guard banding is used to address NBTI, then reliability is improved, but productivity deteriorates due to sacrificing chips' initially available performance by as much as 10-15%
Solution Approach 1:
The patent applies preliminary action by proactively turning off the PMOS transistor before NBTI degradation can occur during standby mode. The control circuit detects standby conditions and switches the PMOS to cutoff state in advance, preventing the negative bias stress that causes threshold voltage drift. This eliminates the need for conservative guard banding while maintaining full performance during active operation.
2Reliability
If gate sizing is used to address NBTI, then reliability is improved, but device complexity increases with an area overhead of 10-20%
Solution Approach 1:
The patent applies dynamics by making the PMOS transistor state variable rather than static. Instead of using a larger transistor size to compensate for NBTI effects, the invention dynamically switches the PMOS between on and cutoff states based on operational mode. This temporal variation replaces spatial enlargement, maintaining compact transistor dimensions while achieving reliability improvements through controlled deactivation during standby.
3Reliability
If Vdd and Vt tuning is used to address NBTI, then reliability is improved, but object-generated harmful factors worsen by aggravating NBTI degradation
Solution Approach 1:
The patent applies the extraction principle by removing the harmful negative bias stress condition rather than attempting to compensate for its effects. By taking the PMOS transistor out of the conductive state during standby mode, the invention extracts the source of NBTI degradation (the negative gate bias) from the system. This eliminates the harmful effect at its source instead of using Vdd/Vt tuning which merely masks symptoms while aggravating the underlying degradation mechanism.
Data Source
AI summary
A control circuit comprises a first NOR gate, a first NMOS transistor, and a first PMOS transistor. The control circuit also comprises an output node. The control circuit further comprises a half latch keeper circuit coupled to a gate of the first NMOS transistor and to a gate of the first PMOS transistor. The half latch keeper circuit is configured to keep the output node at a logical 1 during a standby mode. The control circuit additionally comprises an operational PMOS transistor coupled to the output node. An output of the first NOR gate is coupled to a gate of the operational PMOS transistor. The control circuit is configured to turn off the operational PMOS transistor during the standby mode.