Logic Element Pairing in Circuit Design
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Solution Overview
Problem
Conventional circuit design methods for programmable ICs, such as FPGAs and CPLDs, often result in suboptimal implementation areas and resource usage due to the use of greedy algorithms that do not reconsider previous packing choices, leading to suboptimal combination of logic elements.
Innovation Solution
A dual-element packing algorithm that processes a circuit design graph with nodes representing logic elements and edges representing potential pairs, using a matching algorithm to find an optimal packing by identifying and modifying augmenting paths, thereby grouping logic elements into pairs for more efficient implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If greedy algorithms are used to pack logic element pairs during circuit design, then the packing process is fast, but the result is suboptimal in terms of implementation area and resource usage
Solution Approach 1:
The patent implements feedback by repeatedly applying the packing algorithm multiple times with different initial configurations. Each iteration uses the results from previous iterations to refine the packing, allowing the system to escape local optima and converge toward a globally optimal solution. This iterative feedback mechanism transforms the single-pass greedy algorithm into a multi-pass optimization process that maintains speed while improving precision.
Solution Approach 2:
The patent applies preliminary action by performing initial packing operations with greedy algorithms to establish a baseline configuration, then using these preliminary results as the starting point for subsequent refinement iterations. This preliminary packing provides a structured foundation that guides the optimization process, enabling the algorithm to efficiently explore better configurations without starting from scratch each time.
2Productivity
If greedy algorithms are used to combine logic elements, then the computation is efficient, but the resource utilization is suboptimal
Solution Approach 1:
The system uses feedback by measuring resource utilization after each packing iteration and using this information to guide subsequent iterations. The algorithm monitors which logic elements are underutilized and adjusts packing decisions in later iterations to better utilize available resources, thereby improving overall resource utilization while maintaining computational efficiency through the iterative refinement approach.
Solution Approach 2:
The patent introduces dynamics by making the packing algorithm adaptive across iterations. Rather than using a fixed greedy approach, the algorithm dynamically adjusts its behavior based on results from previous iterations, modifying packing decisions to improve resource utilization. This dynamic adaptation allows the system to transition from a static efficient-but-suboptimal approach to a dynamic approach that balances efficiency with optimal resource usage.
3Device complexity
If logic elements are packed using conventional methods, then the design process is simple, but the implementation area is larger than necessary
Solution Approach 1:
The patent applies preliminary action by first performing a simple greedy packing to establish an initial design configuration, then systematically refining this preliminary result through multiple iterations. This approach maintains the simplicity of the initial design process while progressively reducing the implementation area through automated refinement, effectively separating the simplicity of the base algorithm from the optimization achieved through iteration.
Solution Approach 2:
The system uses feedback to automatically refine the design without requiring complex manual intervention. Each iteration provides feedback on the current implementation area and adjusts the packing accordingly, allowing the simple greedy algorithm to progressively improve toward optimality through automated feedback-driven refinement, thereby reducing implementation area while maintaining design process simplicity.
Data Source
AI summary
In an example implementation, a method of implementing a circuit design for an integrated circuit (IC), includes: on at least one programmed processor, performing operations including: processing a description of the circuit design having logic elements into a graph having nodes representing the logic elements and edges representing potential pairs of the logic elements; determining a packing of pairs of the nodes to divide the graph into selected nodes and unselected nodes and selected edges and unselected edges by performing iterations of: identifying an augmenting path in the graph between a pair of unselected nodes; and modifying the selected nodes and unselected nodes and the selected edges and unselected edges based on the augmenting path; and grouping the logic elements in the description into pairs of logic elements based on the packing of pairs of the nodes.