Distributed Clock Control in Logic Circuit Emulators
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Solution Overview
Problem
In logic circuit emulators with multiple sub-systems, the emulation clock speed cannot be increased, and emulation time cannot be reduced due to the need to stop all sub-systems until all transfer operations are complete, even if some sub-systems have no signal changes or can complete transfers quickly.
Innovation Solution
Implementing a system where each sub-system independently controls its emulation clock, allowing it to advance if there are no transfer requests and no signal changes, and using permission notifications to synchronize clock cycles between sub-systems, thereby reducing the need for a global control circuit to halt all clocks during signal transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global control circuit stops all sub-systems during signal transfers to maintain synchronization, then processing integrity is maintained, but emulation clock speed cannot be increased and emulation time increases
Solution Approach 1:
The global control circuit is segmented into individual clock control units distributed across each sub-system. Each sub-system independently controls its own clock based on local transfer requests and permission notifications, eliminating the need for centralized coordination and allowing parallel operation of multiple sub-systems.
Solution Approach 2:
The clock control system transitions from a static global stop-all approach to a dynamic local control mechanism. Clocks are stopped only in sub-systems that require signal transfers, while other sub-systems continue operating, enabling adaptive and flexible clock management based on actual system state.
2Reliability
If all sub-systems must wait for transfer completion before advancing clocks, then signal transfer accuracy is ensured, but productivity decreases
Solution Approach 1:
Permission notifications are sent in advance to indicate when a sub-system is ready to receive signals. This allows clock control units to proactively stop clocks only when necessary, rather than waiting for transfer completion, thereby maintaining accuracy while improving throughput.
Solution Approach 2:
Sub-systems that do not require signal transfers continue advancing their clocks without interruption. This ensures continuous useful action in those sub-systems while only pausing specific sub-systems that need signal transfers, maximizing overall emulation productivity.
3Ease of operation
If a centralized global control circuit manages all clocks, then coordination is simplified, but device complexity increases due to extensive control signal interconnections
Solution Approach 1:
The centralized global control circuit is divided into distributed clock control units, with each unit managing its local sub-system's clock. This segmentation eliminates the need for extensive interconnections between the global controller and each sub-system, reducing device complexity while maintaining coordination through local permission notification exchange.
Solution Approach 2:
Each sub-system's clock control unit independently manages its own clock based on local transfer requests and received permission notifications. This self-service approach eliminates the need for a centralized controller to directly manage each clock, reducing control signal interconnections and device complexity.
Data Source
AI summary
A logic circuit emulator comprises multiple sub-systems, in which each sub-system outputs to another one of the sub-systems a permission notification to permit the another sub-system to proceed to next emulation clock cycle depending on whether or not the state of an own sub-circuit has advanced. In case a signal that is output from an own sub-circuit and that is to be sent to a sub-circuit of the other sub-system has changed, each sub-system outputs a transfer request to transfer the signal to the another sub-system before the next emulation clock cycle. In case a signal is not being sent from the own sub-circuit to the sub-circuit of the another sub-system, and a permission notification is received but no transfer request is being received from the other sub-system, a clock signal is output for the own sub-circuit to advance the own sub-circuit to the next emulation clock cycle.