Logic Encryption Circuit Using Fault Analysis for IC Security
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Solution Overview
Problem
The semiconductor industry faces significant losses due to reverse engineering, IP piracy, and malicious circuit insertion during the distributed IC design flow, where existing logic encryption methods are ineffective in concealing functionality and preventing attacks, especially with performance overheads from memory elements and RSA units.
Innovation Solution
The integration of combinational logic encryption using XOR/XNOR gates, guided by fault analysis and simulation techniques, to ensure that a wrong key affects 50% of output bits, combined with Physical Unclonable Functions (PUFs) for unique user keys, and a simple Logic Encryption Cell (LEC) to reduce overhead, facilitating secure IC operation without revealing functionality during untrusted phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic encryption is applied to conceal IC functionality during distributed design flow, then security against reverse engineering and IP piracy is improved, but device complexity and performance overhead increase due to additional encryption circuits
Solution Approach 1:
The patent extracts the essential encryption function into a dedicated Logic Encryption Cell (LEC) that can be selectively inserted only at critical points in the design flow where security is needed, rather than encrypting the entire circuit. This extraction approach maintains security while minimizing the added complexity to the overall system.
Solution Approach 2:
The Logic Encryption Cell is designed as a universal component that can be applied to different types of logic circuits and design flows. The LEC provides multi-functionality by serving both as an encryption mechanism and as a security verification point, reducing the need for separate security circuits and thereby limiting complexity growth.
2Reliability
If memory elements and RSA units are used for logic encryption, then security is improved, but performance overhead in terms of area, power, and delay increases significantly
Solution Approach 1:
The patent replaces expensive, high-overhead components like RSA units with simpler, lightweight encryption logic implemented through basic logic gates in the LEC. This substitution uses computationally lighter operations that consume less energy and occupy less area, while still providing adequate security for the design flow protection needs.
Solution Approach 2:
The patent removes memory elements from the encryption architecture and extracts only the essential logical encryption function. This extraction eliminates the significant area and power overhead associated with memory-based encryption approaches while maintaining the core security functionality through combinatorial logic operations.
3Loss of information
If existing logic encryption methods are used, then functionality concealment is achieved, but effectiveness against reverse engineering attacks is insufficient
Solution Approach 1:
The patent applies encryption through the LEC at preliminary stages of the design flow, before the circuit is fully synthesized or implemented. This preliminary encryption action obscures the true functionality early in the process, making subsequent reverse engineering attempts ineffective because the attacker encounters encrypted logic that reveals no meaningful information about the final circuit behavior.
Solution Approach 2:
The Logic Encryption Cell acts as an intermediary component between the clear-text design and the final implemented circuit. This intermediary layer transforms the design representation at each stage, providing a buffer that prevents direct analysis of the original functionality while still allowing legitimate progression through the design flow with the appropriate key.
Data Source
AI summary
Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.