Logic Gate Hardening With Voltage-Dividing Transistors Against Aging

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Solution Overview

Problem

Standard cells in logic gates experience premature aging and inconsistent degradation due to voltage stress, which affects the reliability and performance of digital systems, particularly in mission-critical applications like IoT and automotive systems.

Innovation Solution

A method and system that identify transistors with high voltage swings and couple a voltage dividing transistor to reduce the voltage across them, using a guard-band to avoid timing constraints, thereby extending the life cycle of standard cells and reducing aging effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If standard cells are used in logic gates without modification, then device complexity is low, but premature aging and inconsistent degradation occur due to voltage stress

Engineering Contradiction:

Improvetransistor aging resistanceVSAvoidstandard cell structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the voltage stress problem by introducing a voltage dividing transistor that segments the voltage path. This transistor creates separate voltage zones, reducing the voltage swing across critical transistors and thereby mitigating aging effects without fundamentally changing the standard cell architecture

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A voltage dividing transistor is introduced as an intermediary element between the power supply and the critical transistors. This intermediary component regulates and reduces the voltage stress on aging-prone transistors, protecting them from premature degradation while maintaining logic gate functionality

Inventive Principle:

Principle #24Intermediary (Mediator)

2Duration of action of stationary object

If voltage dividing transistors are added to reduce voltage stress, then transistor aging is reduced, but device complexity increases

Engineering Contradiction:

Improvestandard cell life cycleVSAvoidtransistor count

Core Design Contradiction:

Duration of action of stationary objectVSDevice complexity

Solution Approach 1:

The patent applies local quality by selectively adding voltage dividing transistors only to specific standard cells that are identified as having high voltage stress and aging risk. Not all standard cells are modified, allowing the solution to extend cell life cycle where needed while minimizing the overall increase in device complexity across the entire logic gate

Inventive Principle:

Principle #3Local quality

3Reliability

If guard-band is used to avoid timing constraints, then timing reliability is improved, but voltage stress on transistors increases

Engineering Contradiction:

Improvetiming constraint satisfactionVSAvoidvoltage stress

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful effect of guard-band voltage stress into a benefit by using the voltage dividing transistor to actively reduce the voltage swing. The guard-band provides timing reliability, and the voltage dividing transistor compensates for its harmful voltage stress effect, transforming the situation where both timing and voltage requirements conflict into a solution where both are satisfied

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS20240333289A1Method and system for hardening a transistor logic gate

Publication Date: 2024.10.03 INTEL CORP

AI summary

The disclosure is directed to methods, a standard cell, and a system for forming a logic gate with reduced aging including organizing a plurality of transistors to provide a logic function for the logic gate, identifying a least one transistor in the plurality of transistors having a voltage swing to an output above a predetermined threshold, and coupling a voltage dividing transistor to the at least one transistor to reduce a voltage across the at least one transistor such that the voltage dividing transistor lowers a voltage across the at least one transistor.