Logic Gate Camouflaging via Fault Analysis for IC Security
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Solution Overview
Problem
The semiconductor industry faces significant security vulnerabilities due to reverse engineering and IP piracy, particularly in the context of complex System-on-Chip (SoC) manufacturing, where untrusted foundries can insert malicious circuits or steal IP, leading to substantial annual losses.
Innovation Solution
The implementation of a Design-for-Trust (DfTr) camouflaging technique that uses fault analysis to determine and camouflage logic gate locations, replacing them with 'camouflaged' gates that produce incorrect functionality upon reverse engineering, thereby corrupting outputs and making it difficult for attackers to retrieve the correct functionality, utilizing interference graphs and clique analysis to enhance encryption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic gates are camouflaged to prevent reverse engineering, then security against IP piracy is improved, but manufacturing complexity and design complexity increase
Solution Approach 1:
The patent applies preliminary action by pre-selecting candidate logic gates for camouflaging using fault analysis before the actual camouflaging process. The system identifies gates whose malfunction would have minimal impact on circuit output, then pre-determines their camouflaging locations. This preliminary selection reduces the complexity of the subsequent camouflaging implementation by having already optimized the gate selection criteria.
Solution Approach 2:
The patent introduces an intermediary fault analysis mechanism that mediates between security requirements and design complexity. The fault analysis tool acts as an intermediary by evaluating the impact of potential gate camouflaging on circuit functionality, selecting only those gates where camouflaging would not significantly affect output. This intermediary layer filters out high-risk gates, reducing the overall design complexity while maintaining security.
2Reliability
If fault analysis is used to select camouflaged gates, then security against reverse engineering is improved, but computational time and analysis complexity increase
Solution Approach 1:
The patent applies partial action by performing fault analysis on only a subset of logic gates rather than all gates in the circuit. The system identifies and analyzes only those gates that are candidates for camouflaging based on preliminary criteria, rather than exhaustively analyzing every gate. This partial analysis approach significantly reduces computational time while still providing sufficient security through the selection of critical camouflaging locations.
3Difficulty of detecting and measuring
If camouflaged gates are replaced with dummy contacts or vias, then reverse engineering difficulty is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by selectively applying camouflaging techniques only to specific logic gates identified through fault analysis, rather than uniformly camouflaging all gates. Each camouflaged gate location is carefully selected based on its local impact on circuit functionality. This localized approach allows the use of simpler camouflaging structures (dummy contacts or vias) at specific locations without requiring high manufacturing precision across the entire circuit, as only selected local areas need the camouflaging feature.
Data Source
AI summary
Exemplary systems, methods and computer-accessible mediums can be provided that can, for example, determine a camouflaging location(s) of the logic gate(s) using a fault analysis procedure, and can camouflage the logic gate(s) at the location(s) based on the determination. The camouflaging procedure can be performed by replacing the logic gate(s) at the camouflaging location(s) with a further camouflaged gate, which can have a dummy contact(s) or a vias.