Logic Gate Cell Wiring Resistance Reduction
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Solution Overview
Problem
The existing layout design methods for logic circuits result in high resistance and increased chip size due to the use of second and subsequent layer wiring for inter-cell connections, which is inefficient and requires many wiring tracks.
Innovation Solution
The method involves extending input and output wiring patterns to the cell boundaries and forming dummy patterns within the cell, allowing for connections between adjacent cells using first-layer wiring, thereby reducing resistance and eliminating the need for through-holes and additional wiring layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If second and subsequent layer wiring is used for inter-cell connections, then connections between adjacent cells can be established, but the resistance of connection wiring increases and chip size increases
Solution Approach 1:
The patent transitions the wiring connection from vertical (through-holes across layers) to horizontal (first-layer wiring at cell boundaries). By extending input and output wiring patterns to the cell boundaries and forming extended patterns that protrude into adjacent cells, the connection path changes from multi-layer vertical traversal to single-layer horizontal traversal, significantly reducing resistance.
Solution Approach 2:
The patent segments the wiring function: first-layer wiring handles inter-cell connections by extending to boundaries, while second and subsequent layers are reserved for intra-cell connections. This segmentation eliminates the need for through-holes in inter-cell connections and reduces overall wiring resistance.
2Reliability
If second and subsequent layer wiring is used for inter-cell connections, then connections can be established, but the number of wiring tracks increases and chip size increases
Solution Approach 1:
The first-layer wiring serves dual functions: it provides both intra-cell connections and inter-cell connections. By extending the input and output wiring patterns to the cell boundaries and forming extended patterns, the same first-layer wiring structure accomplishes both connection types, eliminating the need for separate second-layer wiring tracks for inter-cell connections.
Solution Approach 2:
The patent merges the inter-cell connection function with the first-layer wiring structure. The extended patterns at cell boundaries allow first-layer wiring to directly connect adjacent cells without requiring additional second-layer wiring tracks, thereby reducing the total number of wiring tracks and chip size.
3Reliability
If patterns are arranged within cell area with margin from cell boundary, then shorts between adjacent cells are prevented, but inter-cell connection efficiency decreases
Solution Approach 1:
The patent resolves the conflict by changing the connection dimension: instead of connecting through vertical through-holes at cell boundaries, connections are made horizontally through extended first-layer wiring patterns that protrude into adjacent cells. This allows patterns to remain within cell areas with margins for short prevention, while connection efficiency is maintained through the extended horizontal wiring paths.
Solution Approach 2:
The extended wiring patterns are formed in advance during the basic cell design stage, protruding into adjacent cells before actual cell placement. This preliminary extension ensures that when cells are arranged, the wiring connections are already positioned for optimal efficiency without requiring patterns to contact cell boundaries, thus preventing shorts while maintaining connection efficiency.
Data Source
AI summary
The basic cell design method of the present invention is a method for carrying out: extended pattern formation for extending the patterns of input wiring and output wiring in the longitudinal direction, forming first extended patterns that extend with a prescribed dimensional width in a direction perpendicular to the longitudinal direction at the ends of the extended patterns, and forming second extended patterns that extend with the prescribed dimensional width from the input wiring and the output wiring at the center of the cell in the longitudinal direction; and dummy pattern formation for subsequently arranging dummy patterns in vacant areas within the cell.