Optimizing Commutative-Associative Logic Gate Input Permutations
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Solution Overview
Problem
In modern VLSI circuit design, the connections to inputs of associative-commutative logic trees do not impact functionality but significantly affect placement and routing quality, leading to wire length and congestion issues during automatic placement and routing.
Innovation Solution
A method and apparatus optimize the permutation of commutative-associative inputs by framing the problem as a bipartite matching formulation, using linear programming to solve for improved connections that reduce wire length and congestion, with iterative optimization phases to refine the circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If inputs to associative-commutative logic trees are connected in arbitrary order, then circuit functionality is preserved, but wire length and routing congestion increase
Solution Approach 1:
The patent applies preliminary action by optimizing the input ordering of associative-commutative logic trees before the placement and routing stages. The system identifies commutative-associative operations and determines optimal input permutations in advance, using cost functions that estimate wire length and routing congestion. This preliminary optimization prepares the netlist with improved connectivity patterns that guide subsequent automated placement and routing tools, reducing the overall wire length and congestion without requiring changes to the circuit's functional logic.
2Ease of manufacture
If input ordering is optimized for wire length, then routing quality improves, but design time increases
Solution Approach 1:
The patent employs parameter changes by modifying the cost function parameters that guide the input ordering optimization. The system uses adjustable weights for different cost components (e.g., wire length, congestion, timing constraints) to balance optimization quality against computation time. By changing these parameters, the system can adapt to different design priorities and time budgets, providing a controllable trade-off between routing quality improvement and additional design time required.
Solution Approach 2:
The patent applies partial action by selectively optimizing only the commutative-associative portions of the circuit rather than the entire netlist. The system identifies specific logic trees with commutative-associative operations and applies optimization only to those subcircuits, leaving the rest of the design unchanged. This partial optimization approach reduces the computational burden compared to full netlist optimization while still achieving meaningful improvements in routing quality for the targeted portions.
3Manufacturing precision
If commutative-associative input permutations are optimized, then placement and routing quality improve, but computational complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the circuit into independent commutative-associative logic trees and optimizing each tree's input ordering separately. The system traverses the netlist to identify distinct logic trees with commutative-associative operations, then applies optimization algorithms to each tree independently. This segmentation reduces the overall computational complexity compared to optimizing the entire circuit as a single unit, while still achieving improved placement and routing quality through localized optimizations.
Solution Approach 2:
The patent applies preliminary action by performing a traversal of the netlist to identify and categorize commutative-associative logic trees before applying optimization algorithms. This preliminary analysis phase prepares the data structures and cost functions needed for subsequent optimization, organizing the circuit into manageable units with known optimization opportunities. By preparing this information in advance, the system reduces the computational burden during the actual optimization phase.
Data Source
AI summary
A method of optimizing a netlist for a circuit comprising identifying a logic tree with a single output and a plurality of interchangeable inputs, and calculate the optimal permutation of the plurality of inputs. The method further comprising modify the netlist based on the optimal permutation, and optimizing the modified netlist.