Logic Gate Leakage Potential Optimization
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Solution Overview
Problem
Conventional leakage power optimization techniques are inefficient and often result in poor quality of results due to the complexity of semiconductor integration, where a tradeoff exists between transistor speed and leakage power, making it challenging to minimize leakage power without violating performance requirements or electrical design rules.
Innovation Solution
A system that determines leakage potentials for logic gates in a circuit design, orders them based on these potentials, and applies transformations to reduce leakage power while ensuring design requirements are not violated, using a processing order that prioritizes logic gates with higher leakage potential values and employing local and global context evaluations to select appropriate transformations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional leakage power optimization techniques are applied to transform every logic gate, then leakage power reduction opportunities are explored, but computation time becomes excessively long and quality of results deteriorates
Solution Approach 1:
The patent segments the logic gates into different processing groups based on their topological levels and leakage potentials. Instead of processing all gates uniformly, the system divides them into levels (based on signal propagation distance) and further prioritizes within each level, enabling efficient batch processing that reduces computation time while maintaining optimization quality.
Solution Approach 2:
The patent performs preliminary classification of logic gates by determining their leakage potentials and assigning them to processing groups before the actual optimization transformations are applied. This preliminary organization allows the system to prioritize high-impact gates first and avoid unnecessary processing of low-priority gates, significantly reducing overall computation time.
2Productivity
If logic gates with high leakage potential are prioritized for transformation, then leakage power reduction efficiency improves, but risk of violating design requirements increases
Solution Approach 1:
The patent applies different processing strategies to different groups of logic gates based on their local characteristics. High-potential gates are processed with aggressive transformations, while lower-potential gates use more conservative approaches. Each gate's transformation is evaluated in the context of its local circuit environment, ensuring design requirements are met while maintaining high optimization efficiency.
Solution Approach 2:
The system incorporates feedback mechanisms where each transformation attempt is evaluated for compliance with design requirements (timing, area, power constraints). If a transformation violates requirements, the system learns from this feedback and adjusts subsequent transformation selections, ensuring reliability while maintaining optimization progress.
Data Source
AI summary
Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order.