Logic Gate Output Loading Estimation via Network Parameters
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Solution Overview
Problem
Existing circuit simulation techniques require time-consuming iterative calculations to accurately determine the effective capacitance (Ceff) of a logic gate's output load, often resulting in overly pessimistic or optimistic delay simulations due to the use of approximations.
Innovation Solution
A computer system calculates effective capacitance based on total resistance, total capacitance, and geometric parameters of the output network, using a piecewise linear relationship and look-up tables to determine electrical characteristics like input capacitance and delay, which can be applied to series-coupled stages for path delay calculation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If detailed iterative calculations based on poles and zeros are used to determine effective capacitance, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent transforms the effective capacitance calculation from a complex iterative process involving poles and zeros into a direct parameter-based formula. By changing the approach to use total resistance (R), total capacitance (C), and fanout count (F) as input parameters, the computation becomes O(1) rather than iterative, resolving the time-accuracy tradeoff.
Solution Approach 2:
The patent creates a simplified model that copies the essential behavior of the complex iterative calculation without reproducing its computational complexity. The formula Ceff = k × R × C / F captures the key relationships between circuit parameters and effective capacitance, providing accurate results without the time-consuming iterative process.
2Device complexity
If extremum values (minimum and maximum Ceff) are used for approximation, then device complexity is reduced, but measurement precision deteriorates due to overly pessimistic or optimistic delay simulations
Solution Approach 1:
Instead of using extremum values (minimum/maximum Ceff) as approximations, the patent introduces a new parameter-based formula that directly computes a single accurate Ceff value. This changes the approximation approach from using boundary values to using a calculated intermediate value that accurately represents the actual effective capacitance, eliminating the pessimistic/optimistic bias in delay simulations.
Data Source
AI summary
Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to analyze an electrical characteristic of a logic gate electrically coupled to an output network in a stage. In particular, during the analysis, the effective capacitance of an output network coupled to a logic gate is approximated as a function of a total resistance of the output network, a total capacitance of the output network, and a geometric parameter of the output network. Using the effective capacitance and other parameters, such as a slew rate of an electrical signal applied to an input of the logic gate, an electrical characteristic of the logic gate, such as an input capacitance, is determined.