Logic Gate Test Pin Switching for Fast Fault Insertion
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Solution Overview
Problem
Traditional fault insertion testing in stimulated circuits is time-consuming due to the requirement of multiple components and physical rework, making it inefficient.
Innovation Solution
The use of ultra-configurable logic gates with an additional test pin and a low-ohm resistor allows for quick fault insertion testing by converting logic gates between buffer and inverter configurations without physical rework, utilizing a test fixture to drive the test pin high or low.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fault insertion testing is performed using multiple components and physical rework, then the testing can be conducted, but the process becomes time-consuming and inefficient
Solution Approach 1:
The patent incorporates a test pin and low-ohm resistor into the circuit design before production, preparing the circuit for future fault insertion testing without requiring physical rework during the testing phase. This preliminary configuration enables rapid fault testing by allowing direct electrical connection to logic gate inputs, eliminating time-consuming manual modifications.
2Reliability
If multiple components are added to connect to stim circuit for fault testing, then fault testing can be performed, but the device complexity increases
Solution Approach 1:
The patent extracts the fault insertion testing capability from the main circuit operation by providing a separate test pin that connects directly to the logic gate input. This separation allows fault testing to be performed independently without adding multiple components to the main signal path, reducing overall device complexity while maintaining testing capability.
Solution Approach 2:
The low-ohm resistor serves as an intermediary element between the test pin and the logic gate input. This single intermediary component enables fault insertion testing by allowing external test signals to be injected without requiring multiple connection points or complex test equipment interfaces, thereby simplifying the overall system.
3Adaptability or versatility
If physical rework is performed on logic gates to change configuration, then buffer/inverter conversion can be achieved, but the process becomes time-consuming
Solution Approach 1:
The logic gate is designed with an additional input pin and low-ohm resistor configuration built-in during manufacturing, preparing it for both buffer and inverter modes. This preliminary design eliminates the need for physical rework during configuration changes, as the gate can be rapidly reconfigured by simply changing the electrical state of the test pin.
Solution Approach 2:
The patent makes the logic gate configuration dynamic rather than static by enabling easy switching between buffer and inverter modes through electrical control of the test pin. This dynamic configurability allows the logic gate to adapt its function without physical modification, significantly reducing rework time while maintaining versatility.
Data Source
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AI summary
A logic gate system for fault insertion testing can include a logic gate module (101) having a plurality of input pins (1-6). The plurality of input pins can include an input signal pin (5) configured to receive an input signal, a power supply input pin (2) configured to receive power from a power supply, and a test input pin (6). The logic gate module (101) can also include an output pin (7) connected to the input pins via one or more logic gates (101a-101e). The logic gate system can include a power supply line (107) connected to the power supply input pin (2) and the test input pin (6). The logic gate system can also include a zero-ohm jumper resistor (109) disposed between the power supply input pin (2) and the test input pin (6). The zero-ohm resistor (109) can be configured to be replaced with a low ohm resistor to allow reverse driving a voltage on the test input pin (6). The one or more logic gates (101a-101e) can be configured to reverse an output at the output pin (7) when the voltage on the test input pin (6) is reverse driven.