Logic Gate Hardening With Voltage Division Against Transistor Aging
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Solution Overview
Problem
Standard cells in logic gates, particularly CMOS transistors, experience premature aging due to voltage swings, leading to inconsistent degradation across transistors, which affects the reliability and performance of digital systems.
Innovation Solution
A method and system that identify transistors with voltage swings above a predetermined threshold and couple a voltage dividing transistor to reduce the voltage across these transistors, using a guard-band to avoid timing constraints, thereby extending the life cycle of standard cells by reducing aging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are organized in standard logic gates, then logic function is achieved, but voltage swings cause premature aging and inconsistent degradation
Solution Approach 1:
A voltage dividing transistor is introduced as an intermediary element between the power supply and the original transistor. This intermediary transistor divides the voltage swing, exposing only a portion of the total voltage range to the original transistor, thereby reducing hot carrier effects and extending transistor life while maintaining logic functionality.
Solution Approach 2:
The patent changes the voltage parameter by introducing a voltage dividing transistor that modifies the voltage swing experienced by the original transistor. By adjusting the voltage distribution through the dividing transistor, the effective voltage stress on the original transistor is reduced, mitigating aging effects.
2Reliability
If voltage dividing transistor is added to reduce voltage, then aging is reduced, but device complexity increases
Solution Approach 1:
The voltage stress is segmented by introducing a voltage dividing transistor that splits the total voltage swing into multiple smaller segments. The original transistor experiences only a portion of the voltage swing, while the dividing transistor absorbs the remaining stress, effectively segmenting the degradation burden.
3Reliability
If guard-band is used to avoid timing constraints, then timing reliability is improved, but voltage reduction effectiveness is limited
Solution Approach 1:
The voltage dividing transistor is configured to provide partial voltage reduction that is sufficient to mitigate aging effects while staying within timing constraints. Rather than maximizing voltage reduction, the design applies just enough voltage division to achieve the aging mitigation goal without compromising timing performance.
Data Source
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AI summary
The disclosure is directed to methods, a standard cell, and a system for forming a logic gate with reduced aging including organizing a plurality of transistors to provide a logic function for the logic gate, identifying a least one transistor in the plurality of transistors having a voltage swing to an output above a predetermined threshold, and coupling a voltage dividing transistor to the at least one transistor to reduce a voltage across the at least one transistor such that the voltage dividing transistor lowers a voltage across the at least one transistor.