Logic Group Power and Clock Gating for Leakage Reduction
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Solution Overview
Problem
Current clock-gating techniques effectively reduce dynamic power consumption in integrated circuits but fail to address leakage power, as they maintain the full power supply voltage across devices, leading to significant static power consumption in high-performance processors and technology nodes.
Innovation Solution
Implementing fine-grained dynamic power and clock-gating control in integrated circuits with logic groups, each comprising a launch FF, a capture FF, and a logic cloud, using a power switch with a control node between logic groups and their power supply, and a power and clock-gating control block to generate signals that disable switching and turn off power to non-contributing logic groups during clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock-gating is used to reduce dynamic power consumption, then dynamic power is reduced, but leakage power remains significant because full power supply voltage is still applied across devices
Solution Approach 1:
The patent segments the power supply network into multiple independent domains, each可控 by its own power switch. This allows selective power gating at the logic group level rather than applying power globally, enabling simultaneous reduction of both dynamic and leakage power by isolating inactive logic groups from the power supply while maintaining power to active groups
Solution Approach 2:
The patent implements dynamic power supply control where power switches are dynamically enabled or disabled based on the activity status of logic groups. The control logic continuously monitors logic group activity and adjusts power supply accordingly, transitioning from static full-power supply to dynamic adaptive power supply that matches actual computational needs, thereby reducing leakage in inactive regions
2Loss of energy
If power gating is performed globally at hardmacro level, then leakage power is reduced, but fine-grained control is lost
Solution Approach 1:
The patent divides the hardmacro into multiple finer-grained logic groups, each with its own power switch and control logic. This segmentation enables independent power control of small logic units rather than gating entire hardmacros, achieving fine-grained leakage reduction without excessive complexity by limiting the scope of each control unit to a small logic group
Solution Approach 2:
The patent applies power gating selectively to only those logic groups that are inactive, rather than gating entire hardmacros or using excessive control overhead. By gating power at the minimal necessary granularity (logic group level) and only when needed, the patent achieves effective leakage reduction with acceptable complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces both dynamic and leakage power consumption by selectively disabling power to logic groups that do not contribute to the IC's result, achieving energy savings while maintaining performance, with demonstrated energy savings of 37% to 46% and a minimal increase in die area.
Implementation Method 1
at least one power switch having a control node in series between respective logic groups and their positive or negative power supply node
Data Source
AI summary
An IC includes logic groups each including a launch and a capture FF with a logic cloud in between. A power switch is in series with a power supply node of the logic groups. The logic groups have a clock-gating and power control (PCGC) block for dynamically generating a power supply enable (PS_EN) signal output coupled to a control node of the power switch and a clock output (CLK_OUT) signal coupled to a clock input of the launch or capture FF for clocking the logic groups. The PCGC blocks receive an EN signal and a CLK_IN signal and dynamically generate the PS_EN signal and CLK_OUT signals. During clock cycles at least one logic group(s) does not contribute to an intended logic result for the IC the CLK_OUT signal disables switching of at least a portion of the logic group(s) while the PS_EN signal turns off power to the logic group(s).