Logic Circuit Holding Unit Layout for Low-Power Product-Sum Operation
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Solution Overview
Problem
As the complexity and size of artificial neural networks increase, they face challenges with high power consumption and heat generation, which can affect the characteristics of circuit components and make them sensitive to environmental temperatures.
Innovation Solution
A semiconductor device is designed with a hierarchical artificial neural network architecture that includes specific transistors and logic circuits with metal oxide channels, along with holding units and load circuits, to manage signal inversion, switching, and resistance changes, optimizing power usage and temperature resilience.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of circuits in the artificial neural network is increased to improve processing capability, then the calculation performance is improved, but the power consumption and heat generation increase
Solution Approach 1:
The patent divides the artificial neural network into multiple layers (first layer with first neurons, second layer with second neurons, etc.) and implements hierarchical processing. Each layer processes signals independently, allowing the system to handle complex calculations while managing power consumption through structured organization of computational units.
Solution Approach 2:
The patent implements signal transmission in discrete time periods, where signals are transmitted from the first layer to the second layer at specific intervals. This periodic action allows for efficient resource utilization and reduces continuous power consumption while maintaining calculation performance.
2Productivity
If the number of circuits in the artificial neural network is increased to improve processing capability, then the calculation performance is improved, but the heat generation increases and affects circuit characteristics
Solution Approach 1:
By segmenting the neural network into multiple hierarchical layers, the patent distributes heat generation across different spatial zones rather than concentrating it in a single unit. This segmentation allows for better thermal management and reduces the impact of heat on individual circuit characteristics.
Solution Approach 2:
The patent introduces signal transmission mechanisms that act as intermediaries between computational layers, allowing signals to be processed and transmitted efficiently while minimizing direct thermal interaction between adjacent circuit components. This intermediary approach helps isolate thermal effects.
3Adaptability or versatility
If the artificial neural network is made more complex with more layers and neurons, then the processing capability is improved, but the amount of calculation becomes enormous
Solution Approach 1:
The patent segments the computational task into discrete layers, where each layer performs specific processing functions. This segmentation reduces the complexity of individual calculation units while maintaining overall processing capability through hierarchical organization.
Solution Approach 2:
The patent implements dynamic signal transmission between layers, where the activation and deactivation of neural connections can be controlled based on processing needs. This dynamic approach allows the system to adapt calculation complexity to actual processing requirements, reducing unnecessary computations.
Data Source
AI summary
A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data.