Semiconductor Logic Leakage Detection via Voltage Sequencing

The patent applies preliminary action by first writing test data to the logic units before reducing power. This prepares the device in a known state with stored data that can later be read to detect leakage. The sequence of writing data first, then reducing power, allows the leakage detection to compare against a known good state, enabling detection of tiny current leakage that would be invisible in normal operation.

The patent changes the power parameter by reducing it to a low level after writing test data. This parameter change creates conditions where tiny current leakage becomes detectable through subsequent read operations. By controlling the power state transition and timing, the method enables leakage detection that cannot be achieved under normal operating conditions.

The patent performs preliminary data writing to logic units before reducing power. This establishes a known data state that serves as a reference for later comparison. By having the data written first, the system can detect leakage by comparing the read-back data against the originally written data, ensuring reliability through verification rather than blind assumption.

The patent implements feedback by reading back the data from logic units after power reduction and comparing it with the originally written data. This feedback loop provides verification that data was retained during the low-power interval, or identifies leakage by detecting data corruption. The comparison mechanism provides definitive feedback on whether leakage occurred, resolving the reliability concern.