Digital Noise Filter with Logic-Level Gated Clock Control
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Solution Overview
Problem
Conventional digital noise filter circuits consume excessive power as DFFs operate continuously, regardless of noise presence or input signal changes, and power consumption increases with extended noise removal width.
Innovation Solution
A digital noise filter circuit with a gating clock generating circuit that compares input and output signal logic levels, halting the gating clock when levels coincide, and a noise filter circuit using this gating clock for noise removal, reducing power consumption and enabling immediate filtering upon input signal changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DFFs operate continuously to ensure noise removal, then noise filtering reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by controlling DFFs to operate only when needed. The operating clock is supplied to DFFs based on detection of signal changes or noise conditions, rather than continuously. This allows the system to maintain noise filtering reliability when required while reducing power consumption during stable operating conditions.
2Reliability
If the number of DFFs is increased to extend noise removal width, then noise filtering capability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent applies dynamics by making the DFF configuration adaptable. Instead of using a fixed large number of DFFs for all conditions, the system dynamically activates only the necessary number of DFFs based on the actual noise conditions and signal stability. This reduces device complexity while maintaining noise filtering capability when needed.
3Reliability
If DFFs operate continuously, then signal changes are not missed, but power consumption increases
Solution Approach 1:
The patent implements feedback mechanisms to monitor signal conditions and control DFF operation accordingly. By detecting signal changes and noise conditions, the system activates DFFs only when necessary to maintain signal detection accuracy, rather than operating continuously. This feedback-based control reduces power consumption while preserving reliable signal detection.
Data Source
AI summary
A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output signal of the noise filter circuit. The gating clock generating circuit supplies a gating clock as an operating clock to the noise filter circuit when the logic levels of both signals do not coincide, and halts supply of the gating clock when the logic levels of both signals do coincide. The noise filter circuit removes noise from the input signal and outputting the resultant signal as the output signal.