Logic-Locked IC Key Swapping to Block Scan-Chain Key Theft
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Solution Overview
Problem
Existing logic locking technologies are vulnerable to attacks that target the retrieval of the correct key, which can unlock chips and reveal design functionality, and current countermeasures fail to adequately protect the logic locking key from unauthorized access through scan chains.
Innovation Solution
A system and method that swaps the correct key with an incorrect key upon detection of test access, using XOR or XNOR gates controlled by key inputs, and randomly replaces inverters with key-gates to modify the logic design, ensuring the correct key is never accessed through scan interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If scan chains are kept enabled for testing and debugging, then chip functionality can be verified and debugged, but the correct key can be accessed and retrieved through the test interface
Solution Approach 1:
The patent applies preliminary action by disabling the scan chains before they can be misused by attackers. The scan disable circuitry is activated during normal operation to prevent any test access to the logic-locked circuit, thereby securing the key before potential threats can exploit the test interface
Solution Approach 2:
The patent introduces a scan disable circuitry as an intermediary component that mediates between the scan chains and the logic-locked circuit. This intermediary block controls access to the scan chains, allowing legitimate testing while blocking unauthorized access to the key, thus resolving the contradiction between testing capability and security
2Reliability
If scan chains are disabled to protect the key, then security is improved, but testing and debugging capabilities are lost
Solution Approach 1:
The patent applies dynamics by making the scan chain enable/disable state controllable and switchable. The scan disable circuitry can be activated or deactivated based on operational mode, allowing the system to dynamically adjust between security mode (scan disabled) and testing mode (scan enabled), thus resolving the contradiction between security and testing capability
Solution Approach 2:
The patent enables testing to be performed before the scan chains are disabled. The system allows manufacturing testing and debugging to occur when scan chains are enabled, then subsequently disables them to secure the key for normal operation, thereby achieving both testing capability and security at different time phases
3Reliability
If countermeasures are added to protect scan chains, then security is improved, but device complexity increases
Solution Approach 1:
The patent extracts the security function from the main logic circuit by implementing a separate scan disable circuitry. This dedicated security module handles key protection independently, removing the burden of complex security measures from the core logic design and thereby improving security without significantly increasing overall device complexity
Solution Approach 2:
The patent applies local quality by implementing security measures only where needed - specifically at the scan chain interface through the scan disable circuitry. Rather than complicating the entire device, the security enhancement is localized to the specific vulnerability point, thus improving security with minimal increase in overall device complexity
Data Source
AI summary
Exemplary system, method, and computer-accessible medium for protecting at least one logic-locked integrated circuit (IC) design can include, for example, receiving a request(s), and swapping a correct key which is configured to unlock the logic-locked IC design(s) with an incorrect key which is configured to corrupt an output(s) of the logic-locked IC design(s) after receipt of the request(s). The request(s) can be a test access request(s). The correct key can be utilized when the logic-locked IC design(s) can be initially powered on. The correct key can be swapped with the incorrect key using multiplexer(s) or register(s). In addition, exemplary system, method, and computer-accessible medium can be provided for logic-locking a logic design by, randomly replacing randomly-selected inverters in the logic design with XOR or XNOR key-gates, and inserting XOR or XNOR key-gates randomly in randomly-selected locations in the logic design where there is no inverter.