Logic Locking FSM for IC Security with Minimal Overhead
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Solution Overview
Problem
Integrated circuits face challenges in protecting against unauthorized access and intellectual property theft due to existing logic locking methods causing timing, area, and power overhead issues.
Innovation Solution
Implementing logic locking using a finite-state machine (FSM) component or register-transfer level (RTL) gating, where the integrated circuit operates only with a correct key, employing integer linear programming to optimize and minimize overhead, and leveraging RTL clock gating to ensure secure operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional logic locking methods are applied to protect integrated circuits, then security against unauthorized access is improved, but timing overhead, area overhead, and power overhead increase
Solution Approach 1:
The patent extracts the security function into a separate, dedicated logic locking component that operates independently from the main circuit logic. This separation allows the security mechanism to be implemented with minimal impact on the original circuit's timing, area, and power characteristics, resolving the contradiction between security protection and device complexity.
Solution Approach 2:
The patent introduces an intermediary logic locking component that acts as a mediator between the secure key and the main circuit operations. This intermediary structure enables security verification without requiring modifications to the existing circuit logic, thereby maintaining original timing and area characteristics while providing robust security protection.
2Reliability
If conventional logic locking methods are applied to protect integrated circuits, then security against unauthorized access is improved, but timing overhead, area overhead, and power overhead increase
Solution Approach 1:
The security function is extracted into a compact, dedicated logic locking component that requires minimal additional area. By separating the security mechanism from the main circuit, the patent achieves robust security protection with less than 0.11% area overhead, as the locking component can be efficiently implemented without duplicating existing circuit structures.
3Reliability
If conventional logic locking methods are applied to protect integrated circuits, then security against unauthorized access is improved, but timing overhead, area overhead, and power overhead increase
Solution Approach 1:
The logic locking component operates periodically, verifying the security key only when necessary (e.g., at initialization or mode transitions) rather than continuously monitoring all circuit operations. This periodic verification approach provides robust security protection while minimizing power consumption, as the locking logic remains in a low-power state during normal circuit operation.
4Device complexity
If logic locking is applied without modifying current design logic, then security protection is achieved with minimal overhead, but additional logic paths and delay are introduced
Solution Approach 1:
The patent segments the circuit into two independent parts: the original design logic and the logic locking component. The locking component is implemented as a separate module that interfaces with the main circuit through minimal connection points. This segmentation allows security verification to occur in parallel with normal circuit operation, eliminating additional timing delay in the critical data paths while maintaining robust security protection.
Data Source
AI summary
Embodiments are provided for providing enhanced protection of an integrated circuit in a computing system by a processor. A logic locking FSM component or a logic locking with RTL gating may be applied to a current design logic to enable and protect operations of an integrated circuit, where the current design logic remains unchanged. The operation of the integrated circuit may be activated based upon providing to the integrated circuit a correct key from the logic locking FSM component or the logic locking with RTL gating.