Logic Compatible Memory Array Page Segmentation
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Solution Overview
Problem
Conventional multiple-times programming (MTP) memory cells face issues with program disturbance and increased chip area due to interconnected erase and program gates, requiring high voltages that affect adjacent rows and columns, leading to larger memory cell sizes and reduced performance.
Innovation Solution
The memory cell array is organized into pages with independent program and erase lines for each row, allowing for page-wise erasing and reduced program disturbance, with bit-lines connected only within columns and disconnected between pages, enabling more efficient voltage application and reduced cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase gates of all memory cells in a column are interconnected and high voltage is applied to erase a selected memory, then the erase operation is achieved, but all the array needs to be erased and program disturbance occurs to other rows and columns
Solution Approach 1:
The patent divides the memory array into multiple independent pages, where each page has its own dedicated erase gate line. This segmentation allows erase operations to be confined to specific pages rather than affecting the entire array. When erasing a selected memory cell, only the corresponding page is erased, preventing program disturbance to other rows and columns while maintaining complete erase functionality within the targeted page.
2Adaptability or versatility
If erase gates are formed of big well regions and electrically disconnected from each other, then different voltages can be applied to rows, but the memory cell size increases
Solution Approach 1:
The patent segments the erase gate structure into page-specific well regions rather than using large interconnected well regions for entire rows. Each page has its own dedicated erase gate line connected to a specific well region, allowing independent voltage application to each page while significantly reducing the area required per memory cell compared to the conventional approach of large disconnected well regions spanning entire rows.
3Ease of manufacture
If conventional MTP memory cell structure is used with interconnected erase and program gates, then the memory cell can be formed, but program disturbance occurs and chip area increases
Solution Approach 1:
The patent applies segmentation to the gate interconnection structure by creating page-specific erase gate lines and program gate lines instead of array-wide interconnected gates. This allows memory cells to be manufactured using standard CMOS processes while reducing the required chip area by approximately 60%, as the gate structures are confined to smaller page-level regions rather than spanning the entire array.
4Reliability
If high voltage is applied to program gates and erase gates in conventional arrays, then programming and erasing operations are achieved, but program disturbance occurs to adjacent rows and columns
Solution Approach 1:
The patent segments the high voltage application to page-level granularity by providing dedicated erase gate lines and program gate lines for each page. When performing program or erase operations, high voltages are applied only to the selected page's gates, confining the electrical field effects to that specific page and preventing program disturbance to adjacent rows and columns while maintaining reliable programming and erasing operations within the targeted page.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces memory cell size by approximately 60% and minimizes program disturbance, allowing for efficient page-wise erasing and improved performance by confining high voltages within specific pages, thereby enhancing the overall efficiency and compactness of the memory array.
Implementation Method 1
Due to the capacitive coupling of the coupling capacitors 106 and 108, a large voltage drop is produced across the two plates of tunneling capacitor 108, resulting in a high electrical field between the two plates.
Implementation Method 2
When the electrical field is sufficiently high for Fowler Nordheim tunneling to occur, electrons in floating gate 110 tunnel through the insulating material between floating gate 110 and the connecting well region 116.
Data Source
AI summary
An array of memory cells arranged in a plurality of rows and a plurality of columns are provided. The array includes a first program line in a first direction, wherein the first program line is connected to program gates of memory cells in a first row of the array; a first erase line in the first direction, wherein the first erase line is connected to erase gates of the memory cells in the first row of the array; and a first word-line in the first direction, wherein the first word-line is connected to word-line nodes of the memory cells in the first row of the array.