Logic-Memory Semiconductor Structure for Computing-in-Memory Access
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Solution Overview
Problem
The access speed of memories falls short in keeping up with the increasing computing speed of processors, leading to the "memory wall" issue, and existing solutions require separate chips for logic circuits and memory cells, complicating communication and hindering performance.
Innovation Solution
A semiconductor structure integrating a logic element and a memory element on the same substrate, with a compatible manufacturing process, allowing for the formation of a computing-in-memory (CIM) structure that alleviates the memory wall issue by enabling direct access and communication between logic and memory elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory and logic circuits are fabricated on separate chips, then manufacturing process compatibility is maintained, but communication complexity increases and access speed decreases
Solution Approach 1:
The patent merges the logic circuit and memory circuit onto a single substrate, eliminating the need for inter-chip communication. The logic element and memory element are fabricated together in the same manufacturing process, allowing direct integration and reducing communication complexity while improving access speed.
Solution Approach 2:
The patent employs a universal manufacturing process that can fabricate both logic circuits and memory circuits using the same material layers and processing steps. The metal layers, dielectric layers, and electrode structures serve dual purposes for both logic and memory functions, achieving multi-functionality through a single fabrication platform.
2Speed
If memory and logic circuits are integrated on the same chip, then access speed improves, but manufacturing process compatibility becomes challenging
Solution Approach 1:
The patent employs a universal manufacturing process that can fabricate both logic circuits and memory circuits using the same material layers and processing steps. The metal layers, dielectric layers, and electrode structures serve dual purposes for both logic and memory functions, achieving multi-functionality through a single fabrication platform.
Solution Approach 2:
The patent adjusts manufacturing parameters such as metal layer thickness, dielectric material composition, and electrode dimensions to accommodate both logic and memory circuit requirements within the same fabrication process. By changing these parameters selectively in different regions of the substrate, the patent achieves compatibility for both circuit types.
3Productivity
If separate chips are used for logic and memory, then fabrication processes can be optimized independently, but production time and cost increase
Solution Approach 1:
The patent merges the logic circuit and memory circuit onto a single substrate, eliminating the need for separate fabrication and packaging processes. This integration reduces the total number of manufacturing steps, decreases production time, and lowers overall manufacturing cost while improving access speed.
Solution Approach 2:
The patent employs a universal manufacturing process that can fabricate both logic circuits and memory circuits using the same material layers and processing steps. This approach eliminates redundant fabrication processes, reduces production time, and improves productivity by achieving both circuit types in a single manufacturing run.
Data Source
AI summary
A semiconductor structure integrating a logic element and a memory element includes a substrate, a logic element and a memory element. The substrate has a first region and a second region laterally adjacent to the first region. The logic element is disposed in the first region of the substrate, and the memory element is disposed in the second region of the substrate. The logic element includes multiple transistors. The memory element includes an upper electrode, a lower electrode, and a dielectric layer disposed between the upper electrode and the lower electrode. The lower electrode includes a first metal layer, and a first copper-phosphorus alloy layer extending along a contour of the first metal layer to surround the first metal layer. The upper electrode includes a second metal layer, and a second copper-phosphorus alloy layer extending along a contour of the second metal layer to surround the second metal layer.