Universal Logic Memory Block With Triple-Gate Feedback Cells
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Solution Overview
Problem
Conventional logic memory technologies face challenges in implementing all basic CMOS logic operations in a single cell, require large numbers of transistors for stable operation, and are difficult to commercialize due to non-silicon material processes, leading to integration and power consumption issues.
Innovation Solution
A universal logic memory block using a triple-gate silicon device with a positive feedback loop, combining logical operation results in a single structure through a CMOS process, enabling binary combinational logical operations and memory functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional logic memory technology uses volatile memory devices (SRAM, DRAM), then stable operation is achieved, but a large number of transistors are required which limits overall area and power consumption
Solution Approach 1:
The patent combines multiple logic functions (AND, OR, NOT, NAND, NOR, XOR, XNOR gates) and memory storage into a single logic memory cell structure. This integration eliminates the need for separate transistor circuits for each logic operation, significantly reducing the overall transistor count and chip area while maintaining stable operation through the unified cell design.
Solution Approach 2:
The logic memory cell is designed as a universal structure that can perform all basic CMOS logic operations and store values simultaneously. By making the cell multi-functional, the patent eliminates the need for dedicated circuits for each logic operation, thereby reducing area and power consumption while achieving stable operation across all logic functions.
2Reliability
If conventional logic memory technology uses nonvolatile memory devices (ReRAM, MRAM, PCRAM), then memory function is achieved, but complex processes using non-silicon materials are required which reduce device uniformity and stability
Solution Approach 1:
The patent employs homogeneous silicon-based CMOS materials and processes for fabricating the logic memory cell, eliminating the need for complex non-silicon material processes. This homogeneous approach ensures high device uniformity and stability while maintaining manufacturability through standard CMOS fabrication techniques.
Solution Approach 2:
The invention replicates the successful silicon-based CMOS process methodology from conventional logic circuits and applies it to the logic memory cell structure. By copying the proven manufacturing process, the patent achieves high device uniformity and stability without requiring complex non-silicon material processes.
3Adaptability or versatility
If previously studied logic memory technologies are used, then some logic operations are implemented, but all basic CMOS logic operations cannot be implemented in a single cell and individual circuits and wiring are required for each logic operation
Solution Approach 1:
The patent merges all basic CMOS logic operations (AND, OR, NOT, NAND, NOR, XOR, XNOR) and memory storage into a single integrated cell structure. This consolidation eliminates the need for separate individual circuits and wiring for each logic operation, achieving high adaptability while reducing device complexity and improving integration.
Solution Approach 2:
The logic memory cell is designed as a universal structure capable of performing all basic CMOS logic operations through selective activation of different transistor configurations. This multi-functionality allows a single cell to replace multiple dedicated circuits, significantly improving integration while maintaining full logic operation capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves processing speed and integration by fusing logical operation and storage functions, reducing power consumption and maintaining logical operation values without structural changes.
Implementation Method 1
a universal logic memory block using a triple-gate silicon device with a positive feedback loop, combining logical operation results in a single structure
Data Source
Figure 1A~1B
Figure 2A
Figure 2B
AI summary
The present disclosure relates to a universal logic memory block using a plurality of universal logic memory cells. The universal logic memory block according to one embodiment of the present disclosure may implement various combinational logical operations in a single structure by combining logical operation results from a plurality of universal logic memory cells using triple-gate silicon devices driven by a positive feedback loop.