Logic and Memory Integration via Selective Gate Cavity Formation

Solution Overview

Problem

The integration of non-volatile memory devices and logic devices on the same substrate is challenging due to the different requirements for charge storage in non-volatile memory devices and high-speed operation in logic devices, particularly because of the need for a floating gate in non-volatile memory devices, which complicates their integration with logic devices using a replacement gate process flow.

Innovation Solution

A semiconductor structure and method that utilize a gate-last process flow to integrate logic and non-volatile memory transistors, where logic transistors have a high-k gate dielectric and gate electrode, and non-volatile memory transistors include a tunnel oxide, floating gate, control oxide, and high-k gate dielectric, allowing for the formation of sacrificial gate stacks and subsequent high-k gate dielectric and gate electrode formation in both types of transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a floating gate is used in non-volatile memory devices to store charge, then non-volatile memory functionality is achieved, but integration with logic devices becomes difficult due to different structural requirements

Engineering Contradiction:

Improvecharge storage capabilityVSAvoidintegration complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The substrate is divided into distinct logic device regions and non-volatile memory device regions, allowing each region to have optimized structures (logic transistors without floating gates, memory transistors with floating gates) while maintaining overall integration. This segmentation enables independent optimization of each device type without compromising the other.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different gate structures are applied to different regions: logic devices use simple gate structures optimized for high-speed operation, while non-volatile memory devices use floating gate structures optimized for charge storage. This local differentiation allows each device type to have the optimal structure for its specific function while being integrated on the same substrate.

Inventive Principle:

Principle #3Local quality

2Speed

If logic devices are designed for high-speed operation, then performance is improved, but integration with non-volatile memory devices is complicated by conflicting structural requirements

Engineering Contradiction:

Improveoperation speedVSAvoidintegration complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The substrate is divided into distinct logic device regions and non-volatile memory device regions, allowing each region to have optimized structures (logic transistors without floating gates, memory transistors with floating gates) while maintaining overall integration. This segmentation enables independent optimization of each device type without compromising the other.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different gate structures are applied to different regions: logic devices use simple gate structures optimized for high-speed operation, while non-volatile memory devices use floating gate structures optimized for charge storage. This local differentiation allows each device type to have the optimal structure for its specific function while being integrated on the same substrate.

Inventive Principle:

Principle #3Local quality

3Speed

If a replacement gate process flow is used for advanced logic technology, then logic device performance is improved, but integration of non-volatile memory devices becomes more difficult

Engineering Contradiction:

Improvelogic device performanceVSAvoidintegration process difficulty

Core Design Contradiction:

SpeedVSEase of manufacture

Solution Approach 1:

Sacrificial gate stacks are formed in advance in both logic and memory regions before the final gate formation steps. These sacrificial structures guide subsequent processing and enable the formation of different final gate structures (simple gates for logic, floating gate structures for memory) through selective removal and replacement steps.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Sacrificial gate stacks serve as intermediary structures that facilitate the integration process. These temporary structures are formed using standard replacement gate process steps, then selectively removed and replaced with appropriate final gate structures for each device type, enabling complex integration through a systematic intermediate step.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20180053773A1Integration of floating gate memory and logic device in replacement gate flow

Publication Date: 2018.02.22 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

After forming a first sacrificial gate stack over a portion of a first semiconductor fin located in a logic device region of a substrate, and a second sacrificial gate stack over a portion of a second semiconductor fin located in a memory device region of the substrate, in which each of the first sacrificial gate stack and the second sacrificial gate stack includes, from bottom to top, a tunneling oxide portion, a floating gate electrode, a control oxide portion, a gate conductor and a gate cap, an entirety of the first sacrificial gate stack is removed to provide a first gate cavity, and only the gate cap and the gate conductor are removed from the second sacrificial gate stack to provide a second gate cavity. Next, a high-k gate dielectric and a gate electrode are formed within each of the first gate cavity and the second gate cavity.