Logic-Memory Chip Architecture for In-Memory Computing
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Solution Overview
Problem
Existing memory devices face inefficiencies in processing performance and power consumption due to the need for external communication between processing resources and memory arrays, which can be addressed by integrating logic and memory components within a single chip to facilitate processing-in-memory (PIM) operations.
Innovation Solution
The integration of logic and memory components within a single chip, utilizing through silicon vias for enhanced signaling, allows for partitioned logic operations to be performed directly on memory arrays, reducing the need for external processing resources and enabling faster, more efficient logical operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processing resources are external to the memory array with data accessed via bus, then device complexity is reduced and manufacturing is easier, but processing performance deteriorates and power consumption increases
Solution Approach 1:
The patent merges processing resources (logic circuits, functional units) directly into the memory array structure, creating a unified memory-processor chip. This integration eliminates external buses and enables processing operations to be performed directly within the memory array, thereby improving processing performance while accepting increased device complexity as a trade-off for achieving PIM capabilities
2Use of energy by stationary object
If data is accessed via external bus between processing resources and memory array, then device complexity is lower, but power consumption increases due to external communications
Solution Approach 1:
By integrating processing resources within the memory array, the patent eliminates power-consuming external bus communications. The merged structure allows data to be processed in-place within the memory array, significantly reducing power consumption associated with data transfer while accepting the complexity of the integrated architecture
3Productivity
If processing resources are integrated internal to memory array, then processing performance improves and power consumption reduces, but device complexity increases
Solution Approach 1:
The patent segments the memory array into multiple banks, with each bank having its own integrated processing resources. This segmentation allows parallel processing operations across different banks, improving overall processing performance while distributing the complexity across modular units that can be managed independently
4Loss of energy
If processing resources are integrated internal to memory array, then power consumption reduces by eliminating external communications, but device complexity increases
Solution Approach 1:
The patent merges processing resources with memory arrays to create a unified structure that eliminates power-consuming external communications. This integration achieves significant power savings by enabling in-place processing, while the resulting device complexity is managed through careful architectural design and segmentation into banks
Data Source
AI summary
Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.