Logic and Memory Cell Rail Layout for Higher Unit Density
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Solution Overview
Problem
Current semiconductor memory devices face limitations in active region density and area scaling due to constrained fin arrangements in logic cells, leading to inefficient use of space and reduced performance.
Innovation Solution
The proposed solution involves arranging multiple fins in logic cells to form more than three transistors, allowing for increased active region density and improved area scaling by optimizing the arrangement of fins and conductive rails in a metal layer, enabling the formation of multiple device units within adjacent logic cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fin arrangements in logic cells are constrained to traditional layouts, then manufacturing simplicity is maintained, but active region density and area scaling are limited
Solution Approach 1:
The logic cell is divided into multiple device units, each containing a specific number of fins (e.g., three fins per device unit). By segmenting the logic cell into adjacent device units with shared fins, the patent achieves higher active region density while maintaining manageable manufacturing complexity through modular design.
Solution Approach 2:
Adjacent device units share common fins, merging structural elements to increase density. For example, a first device unit and a second device unit share fins, allowing the logic cell to achieve higher active region density without proportionally increasing the total number of fins, thus balancing density improvement with manufacturing complexity.
2Productivity
If more fins are arranged in logic cells to form more transistors, then area scaling and performance are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements different fin configurations in different regions of the logic cell. Specific device units have defined numbers of fins (e.g., three fins) with specific spacing relationships, allowing localized optimization of transistor formation while maintaining overall manufacturing feasibility through region-specific design rules.
Solution Approach 2:
The patent varies the number of fins and their spacing parameters across different device units within the logic cell. By changing these geometric parameters locally rather than uniformly, the design achieves improved area scaling and productivity while keeping manufacturing precision requirements within acceptable ranges through controlled parameter variation.
3Area of stationary object
If traditional cell height constraints are applied to peripheral cells, then design rule compliance is maintained, but space utilization and device unit density are reduced
Solution Approach 1:
The patent optimizes the arrangement of fins and device units within the constrained cell height by utilizing horizontal spacing and vertical stacking efficiently. Device units are arranged in adjacent relationships with shared fins, maximizing space utilization within the traditional cell height constraint while achieving higher device unit density through clever two-dimensional layout optimization.
Data Source
AI summary
A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.