Logic-Memory Cell Rail Layout for Higher Active Region Density
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Solution Overview
Problem
Current semiconductor memory devices face limitations in active region density and area scaling due to constrained fin arrangements in logic cells, leading to inefficient use of space and reduced performance.
Innovation Solution
The proposed solution involves arranging multiple fins in logic cells to form more than three transistors, allowing for increased active region density and improved area scaling by optimizing the arrangement of fins and conductive rails in a metal layer, enabling the formation of multiple device units within a smaller area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fins are arranged in logic cells following conventional design rules, then manufacturing process is simple and reliable, but active region density is limited and area scaling is constrained
Solution Approach 1:
The patent transitions from conventional two-dimensional planar fin arrangements to three-dimensional vertically-stacked fin structures. Multiple fins are arranged in vertical columns extending through the substrate, enabling more transistors to be packed into the same footprint area. This dimensional change directly increases active region density without proportionally increasing manufacturing complexity, as the vertical stacking follows established semiconductor fabrication processes.
Solution Approach 2:
The patent implements nested fin structures where multiple fins are positioned within overlapping horizontal projections. The fins are arranged such that their top surfaces are at different vertical levels, creating a nested configuration that maximizes space utilization. This nesting approach allows more active regions to be contained within the same lateral footprint, thereby increasing active region density while maintaining manufacturability through standard deposition and etching techniques.
2Area of stationary object
If more fins are arranged in logic cells to form more transistors, then area scaling is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the logic cell into multiple discrete fin structures that are independently formed but collectively achieve the desired high-density transistor array. Each fin is a separate structural element with defined lateral and vertical dimensions, allowing for modular manufacturing. This segmentation enables better control over individual fin dimensions and positions, thereby managing manufacturing precision requirements while achieving improved area scaling through the cumulative effect of multiple fins.
Solution Approach 2:
The patent employs parameter changes in the fin structures, including varying fin heights, adjusting fin spacing, and modifying fin widths to optimize the balance between density and manufacturability. By carefully controlling these geometric parameters, the design achieves high area efficiency while keeping manufacturing precision within achievable limits for current semiconductor fabrication capabilities.
Data Source
AI summary
A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.