3D Logic-Memory Structure Using Monocrystalline Channels and Vertical Routing
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Solution Overview
Problem
Current 3D memory technologies face challenges with wire performance degradation due to scaling, leading to increased power consumption and reduced functionality in ICs, and existing 3D memory schemes often use poly-silicon channels that suffer from higher cell-to-cell performance variations and lower drive capabilities compared to monocrystalline channels.
Innovation Solution
The development of 3D memory devices with monocrystalline channels constructed using alternative methods beyond ion cut and successive layer transfers, allowing for multiple layers to be processed with a single lithography step, reducing construction costs and improving performance by utilizing oxide-to-oxide bonds and incorporating antifuse structures, power down control circuits, and digital-to-analog converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If poly-silicon channels are used in 3D memory, then manufacturing is easier, but cell-to-cell performance variations increase and drive capability decreases
Solution Approach 1:
The patent changes the material parameter from poly-silicon to monocrystalline silicon for the channel, fundamentally altering the electrical properties to reduce performance variations and improve drive capability while maintaining 3D memory functionality
Solution Approach 2:
The patent employs a composite structure combining monocrystalline silicon channel with oxide layers (such as silicon oxide or high-k dielectrics) to achieve both manufacturing feasibility and improved electrical performance characteristics
2Reliability
If monocrystalline channels are used in 3D memory, then cell-to-cell performance variations decrease and drive capability increases, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional stacked architecture, utilizing vertical stacking of memory layers to achieve high density while maintaining manufacturing compatibility through standard lithography processes
Solution Approach 2:
The patent divides the 3D memory structure into multiple discrete layers (word lines, bit lines, select lines, and memory cells) that can be independently fabricated and then stacked, simplifying the overall manufacturing process while enabling monocrystalline channel implementation
3Productivity
If wires are scaled down to improve transistor density, then transistor performance improves, but wire performance degrades and power consumption increases
Solution Approach 1:
The patent moves interconnect routing from two-dimensional planar layout to three-dimensional vertical stacking, allowing wires to be positioned directly above transistors they serve, thereby reducing wire length and resistance without compromising transistor density
Solution Approach 2:
The patent implements a hierarchical interconnect structure where lower-level interconnects are nested within or adjacent to upper-level interconnects, enabling efficient signal routing through multiple vertical layers and reducing overall wire length and power consumption
Data Source
AI summary
A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit which includes a plurality of first transistors; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors which include a metal gate are disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; and a memory array including word-lines, the memory array includes at least four memory mini arrays, each including at least four rows by at least four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, the memory control circuit includes at least one digital to analog converter circuit.