Face-to-Face Logic-Memory Stacking for Shorter IC Interconnects
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Solution Overview
Problem
Modern integrated circuit (IC) devices face challenges in balancing design goals such as reducing IC package size, improving heat dissipation, and enhancing processing performance while managing cost, particularly in mobile applications with complex interconnect schemes and power constraints.
Innovation Solution
A stacked IC device configuration with face-to-face connections between logic and memory dies, using conductors that extend through the region between memory dies to connect to a substrate, facilitating short interconnect paths and reducing reliance on horizontal connections, thereby improving data rate, power efficiency, and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If more interconnect layers are used to support increased number of devices, then device interconnection capability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar interconnection to three-dimensional vertical interconnection by stacking memory dies and logic dies in multiple layers. Conductors extend vertically through the stack to connect devices across different layers, enabling high-density interconnection without increasing lateral footprint or requiring multiple horizontal interconnect layers.
2Area of stationary object
If IC package size is reduced, then device size constraint is satisfied, but heat dissipation area is reduced
Solution Approach 1:
The patent moves heat dissipation from a two-dimensional surface problem to a three-dimensional volumetric solution by stacking multiple dies vertically. This allows the package footprint to remain small while increasing the internal volume for heat management structures, such as thermal vias and heat sinks that can extend through the stack.
Solution Approach 2:
The patent implements localized heat dissipation structures at specific hot spots within the stack. Thermal management features are strategically placed near high-power logic dies or memory interfaces where heat generation is most intense, rather than uniformly distributing thermal management across the entire package.
3Ease of manufacture
If logic and memory dies are connected through conventional lateral interconnects, then manufacturing is simpler, but interconnect path length increases reducing data rate
Solution Approach 1:
The patent replaces long lateral interconnect paths with short vertical conductors that extend directly between stacked dies. This dimensional transition dramatically reduces the distance signals must travel between logic and memory, improving data rate and power efficiency while simplifying the interconnect structure by eliminating complex lateral routing layers.
Data Source
AI summary
A stacked IC device includes a first memory die and a second memory die coupled to the substrate. The stacked IC device also includes a logic die electrically connected, face-to-face, to the first memory die and the second memory die and electrically connected to the substrate by conductors that extend through a region between the first memory die and the second memory die.