Logic-Memory Cells for Compact Stochastic Computing Circuits

The patent combines the random bit stream generation function and the logical operation function into a single logic-memory cell. The logic-memory cell stochastically transitions between low-resistance and high-resistance states to generate random bits, while simultaneously performing logical operations (AND, OR, NOT) on these bits. This merging eliminates the need for separate random number generator circuits, thereby reducing circuit size while maintaining computational accuracy.

The logic-memory cell is designed to serve multiple functions: it acts as a random number generator by stochastically switching between resistance states, stores computational results in its memory function, and performs logical operations through controlled current flow. This multi-functionality reduces the total number of circuit elements required while preserving the accuracy of stochastic computations.

By merging random bit generation and logical operations into the same logic-memory cell, the patent eliminates redundant circuit elements that would otherwise consume power. The stochastic transitions occur within the intrinsic thermal noise of the device itself, requiring no additional power-hungry random number generator circuits, thus reducing overall power consumption while maintaining computational accuracy.

The logic-memory cell utilizes its own intrinsic thermal noise and stochastic properties to generate random bits without requiring external random number generation circuits. The device serves itself by leveraging its inherent physical characteristics for random bit generation, eliminating the need for separate power-consuming randomization hardware.

The patent merges three distinct functions—random number generation, memory storage, and logical operation execution—into a single logic-memory cell structure. This consolidation dramatically simplifies the overall circuit architecture by eliminating the need for separate random number generator circuits, additional memory elements, and multiple logic gate implementations, thereby reducing device complexity while maintaining full computational capability.

The logic-memory cell is designed as a universal component that can perform random bit generation, data storage, and various logical operations (AND, OR, NOT) within a single device structure. This multi-functionality reduces the total number of discrete components and interconnections required, significantly simplifying the overall circuit design and reducing device complexity.