3D Logic-Memory Tile Stacking for Scalable IC Fabrication
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Solution Overview
Problem
Current semiconductor architecture design and fabrication processes face challenges such as performance mismatch between logic and memory units, high non-recurring engineering (NRE) costs, long production cycles, and limited scalability, leading to inefficient data routing and increased power consumption.
Innovation Solution
The implementation of a 3D stacked integration technology using wafer-to-wafer bonding, where logic and memory tiles are aligned and diced along scribe lines to form integrated circuits (ICs), allowing for flexible dicing and scalable architectures that reduce NRE costs and time-to-market pressures, while enhancing data transmission speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor architecture design and fabrication processes are used, then production cycles are long and NRE costs are high, but performance mismatch between logic units and memory units occurs and data routing efficiency decreases
Solution Approach 1:
The patent transitions from conventional 2D planar integration to 3D stacked integration, bonding a first wafer containing logic tiles with a second wafer containing memory tiles vertically. This dimensional change enables simultaneous optimization of both productivity (through parallel wafer fabrication) and performance matching (through direct vertical interconnection via through-silicon vias), resolving the contradiction between fast production and performance reliability.
2Adaptability or versatility
If logic wafer and memory wafer are bonded with aligned scribe lines for simultaneous dicing, then scalability and flexibility are improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments each wafer into multiple independently designable tiles (logic tiles on the first wafer, memory tiles on the second wafer) separated by scribe lines. This segmentation enables flexible combination and scaling of tiles to create different IC architectures while maintaining manageable manufacturing processes through standardized wafer bonding and alignment procedures.
Solution Approach 2:
The patent creates a universal wafer bonding platform where scribe lines on both wafers are aligned to enable simultaneous dicing into multiple ICs. This universal approach allows the same fabrication and bonding process to produce various IC configurations by simply changing which tiles are selected and combined, enhancing scalability without proportionally increasing manufacturing complexity.
3Speed
If 3D stacked integration with wafer-to-wafer bonding is implemented, then data transmission speed and power efficiency are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates alignment marks and precisely defined scribe lines during the wafer fabrication stage (before bonding). This preliminary action establishes reference features that guide the subsequent wafer bonding process, enabling high-precision alignment through mechanical or optical alignment systems without requiring ultra-precise control during the actual bonding operation, thus achieving fast data transmission while managing manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-performance ICs with improved data transmission speed, reduced power consumption, and increased scalability, addressing the performance mismatch and cost issues in conventional semiconductor design and fabrication.
Implementation Method 1
The logic wafer and the memory wafer are simultaneously diced along the at least one first scribe line and the aligned at least one second scribe line to obtain a plurality of integrated circuits (ICs)
Data Source
AI summary
The present disclosure relates to a system and a method for fabricating one or more integrated circuits (ICs). The system includes a plurality of logic tiles formed on a logic wafer and separated by at least one first scribe line, a respective logic tile including a function unit including circuitry configured to perform a respective function; at least one global interconnect configured to communicatively connect the plurality of logic tiles; a plurality of memory tiles formed on a memory wafer connected with the logic wafer, the plurality of memory tiles separated by at least one second scribe line that is substantially aligned with the at least one first scribe line, wherein the logic wafer and the memory wafer are diced along the at least one first scribe line and the at least one second scribe line to obtain a plurality of ICs, a respective IC including at least one logic tile connected with at least one memory tile.