Logic Circuit Node Verification for Stability and Controllability
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Solution Overview
Problem
Existing circuit design methods struggle to efficiently verify the stability and controllability of nodes in logic circuits due to the large computational burden of direct simulation, especially when nodes do not directly connect to registers.
Innovation Solution
A circuit verification method using a formal method to convert circuit design data into a formal circuit model, employing first-stage and subsequent property commands to identify stable and unstable nodes, reducing the need for exhaustive signal pattern testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If direct simulation method is used to verify node stability, then verification thoroughness is improved, but computational complexity increases significantly
Solution Approach 1:
The verification process is segmented into multiple stages: first-stage formal commands verify basic stability, while second-stage formal commands verify stability under specific input conditions. This segmentation allows comprehensive verification to be divided into manageable parts, reducing the computational burden of each individual verification pass while maintaining overall thoroughness.
Solution Approach 2:
The patent performs preliminary verification using first-stage formal commands to identify nodes that fail basic stability requirements before proceeding to more complex second-stage verification. This preliminary action filters out obviously unstable nodes early, preventing unnecessary computational resources from being wasted on nodes that already fail basic checks.
2Measurement precision
If exhaustive signal pattern testing is performed, then detection precision is improved, but verification time increases
Solution Approach 1:
Instead of performing exhaustive testing on all possible signal patterns, the patent applies partial action by focusing verification efforts on critical nodes identified by the formal method. The formal verification approach provides mathematical guarantees for the tested cases without requiring exhaustive enumeration of all possible input combinations, thus achieving high detection precision with reduced verification time.
Solution Approach 2:
The patent replaces traditional mechanical simulation-based verification with formal method-based verification. The formal method uses mathematical models and logical reasoning to verify node stability, substituting the time-consuming mechanical process of exhaustive signal pattern testing with a more efficient mathematical approach that provides equivalent or superior detection precision.
3Productivity
If formal method is used to reduce computational burden, then productivity is improved, but verification depth may be reduced
Solution Approach 1:
The patent introduces an intermediary approach by combining formal method verification with targeted simulation verification. The formal method serves as the primary verification tool for efficiency, while selective simulation verification acts as an intermediary to provide deeper inspection when needed, thus maintaining both productivity and verification depth.
Solution Approach 2:
The verification approach is made dynamic by adaptively selecting between first-stage and second-stage formal commands based on node characteristics and failure modes. The system dynamically adjusts the verification depth for different nodes, applying more rigorous second-stage verification only where necessary, thus optimizing the balance between productivity and verification depth.
Data Source
AI summary
A circuit verification method, including the following steps: inputting a circuit design data to a processor, wherein the circuit design data includes a plurality of logic circuits and a plurality of detection nodes, each logic circuit includes a control terminal and a plurality of input terminals, and is configured to output a signal to the detection node; inputting a plurality of first-stage property command to the processor to generate a plurality of first-stage formal commands, and the first-stage formal commands are configured to verify whether signals of the detection nodes remain stable when a signals of the control terminal of each of the logic circuits does not changed; finding a first part of the detection nodes by a formal method according to the first-stage formal commands; and finding a second part of the detection nodes by a formal method.