Logic Transistor and NVM Cell Integration via Replacement Gate
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Solution Overview
Problem
There is a need to enhance the performance of integrated circuits that combine non-volatile memory (NVM) and logic functions while minimizing cost increases, particularly in the context of the replacement gate technique, where existing methods struggle to achieve high performance without sacrificing logic performance or incurring additional costs.
Innovation Solution
The integration of a logic transistor and an NVM cell on the same semiconductor substrate using a replacement gate approach, where a high-k gate dielectric and metal gate are employed, with the NVM cell being either a split gate or floating gate type, allowing for two different depositions that align with logic transistor formation, utilizing high-k dielectrics and metal gates to improve performance and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replacement gate process is implemented, then performance enhancement is achieved, but manufacturing complexity increases
Solution Approach 1:
The formation of high-k dielectric layers and metal gate layers is merged into the existing replacement gate process flow. The same deposition and etching steps used for NVM replacement gates are also used for logic transistor gates, consolidating process steps and reducing overall manufacturing complexity.
Solution Approach 2:
The replacement gate process is designed to serve dual purposes: forming high-performance gates in NVM regions and forming gates in logic regions. The process steps and materials are made universal across both region types, reducing the need for separate processing sequences and simplifying manufacturing.
2Reliability
If high-k dielectric and metal gate are used, then performance is improved, but manufacturing cost increases
Solution Approach 1:
High-k dielectric layers are formed preliminarily across the entire substrate before region-specific patterning. This preliminary formation allows subsequent selective removal in logic regions while retaining the layers in NVM regions, avoiding the need for separate high-k dielectric formation processes and reducing overall cost.
Solution Approach 2:
The gate dielectric thickness and material composition are optimized as adjustable parameters: thinner high-k dielectric layers are used in NVM regions where higher performance is needed, while logic regions can use conventional thicker dielectric layers, allowing performance-cost optimization through parameter adjustment rather than universal high-cost implementation.
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
An oxide-containing layer (18) is formed directly on a semiconductor layer (12) in an NVM region (14), and a first partial layer (20) of a first material is formed over the oxide-containing layer in the NVM region. A first high-K dielectric layer (22) is formed directly on the semiconductor layer in a logic region (16). A first conductive layer (24) is formed over the first dielectric layer in the logic region. A second partial layer (26) of the first material is formed directly on the first partial layer in the NVM region and over the first conductive layer in the logic region. A logic device is formed in the logic region. An NVM cell is formed in the NVM region, wherein the first and second partial layer together are used to form one of a charge storage layer (28) if the cell is a floating gate cell or a select gate (28) if the cell is a split gate cell.