Logic Obfuscation Key-Gate Placement via Interference Graph
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Solution Overview
Problem
Integrated circuits (ICs) are vulnerable to reverse engineering and IP piracy due to untrusted design phases in the globalization of IC design, leading to significant annual losses in the semiconductor industry, as attackers can reverse-engineer functionality, steal IP, and insert malicious circuits without designers' knowledge.
Innovation Solution
The implementation of a logic obfuscation technique using key-gates inserted strategically into the IC design flow, where the correct key is required for the IC to function correctly, and incorrect keys result in incorrect outputs, with the use of an interference graph to determine optimal key-gate locations and types, such as XOR or XNOR gates, to hinder key determination by attackers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic obfuscation is applied to protect IC functionality, then security against reverse engineering is improved, but device complexity increases due to insertion of additional key-gates
Solution Approach 1:
The patent applies obfuscation selectively at specific locations within the IC design rather than uniformly across the entire circuit. Key-gates are inserted at strategically chosen points where they provide maximum security benefit with minimum impact on overall circuit complexity. This localized approach allows the designer to protect critical functionality while maintaining simplicity in non-critical areas.
Solution Approach 2:
The obfuscation mechanism is divided into separate key-gates that can be independently inserted and managed. Each key-gate operates as an independent security module, allowing the complexity to be segmented and distributed throughout the design rather than concentrated in one location. This segmentation makes the system more manageable and allows for selective application of obfuscation strength.
2Reliability
If multiple key-gates are inserted to increase key space, then security strength is improved, but manufacturing complexity increases
Solution Approach 1:
The key-gate design uses universal gate structures (such as XOR or XNOR gates) that can be repeatedly instantiated throughout the design without requiring custom circuitry for each instance. This multi-functional approach allows the same basic gate structure to serve multiple security purposes at different locations in the IC, simplifying the manufacturing process while maintaining strong security through the combination of multiple instances.
3Reliability
If key-gates are strategically positioned to maximize security, then resistance to key determination attacks is improved, but design time and complexity increase
Solution Approach 1:
The patent performs strategic positioning of key-gates during the design phase using automated tools that analyze the circuit and identify optimal insertion points before fabrication. This preliminary action ensures that key-gates are placed at locations that maximize security (such as points that control critical signal paths or protect sensitive IP) without requiring time-consuming manual optimization later. The automated analysis completes the positioning task efficiently, reducing overall design time.
4Reliability
If obfuscation is applied throughout the entire design flow, then IP protection is improved, but productivity is reduced due to increased processing requirements
Solution Approach 1:
Rather than applying obfuscation to every component and signal path in the IC design, the patent applies key-gates selectively to the most critical portions of the design that contain valuable IP or sensitive functionality. This partial action approach provides sufficient IP protection for the most important assets while avoiding the excessive processing requirements and productivity loss that would result from universal obfuscation application throughout the entire design flow.
Data Source
AI summary
Exemplary systems, methods and computer-accessible mediums for encrypting at least one integrated circuit (IC) can include determining, using an interference graph, at least one location for a proposed insertion of at least one gate in or at the at least one IC, and inserting the gate(s) into the IC(s) at the location(s). The interference graph can be constructed based at least in part on an effect of the location(s) on at least one further location of the IC(s).