3D Logic-Passive Stack Using TOVs for Higher IC Density
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing transistor density due to physical limitations and complexity in manufacturing, particularly in arranging both logic and passive devices within a limited area on a substrate.
Innovation Solution
A novel integrated logic and passive device structure is proposed, where passive devices are stacked on the backside of logic devices, utilizing a gate-all-around (GAA) MOSFET process with a SOI or epitaxial SiGe/Si substrate, and connected via through oxide vias (TOVs) to enhance integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If passive devices and logic devices are arranged side by side on the front side of the substrate, then the manufacturing process is simpler, but the integration density and transistor density are limited due to area constraints
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional vertical stacking by moving passive devices to the backside of the substrate. Logic devices remain on the front side while passive devices are formed on the backside, utilizing the third dimension (vertical depth) to increase integration density without increasing the chip footprint area.
Solution Approach 2:
The substrate is divided into front and back sides with distinct functional regions. The front side contains logic devices while the back side contains passive devices, separating different device types into different spatial zones. This segmentation allows each side to be optimized independently while increasing overall integration capacity.
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency improves and costs decrease, but manufacturing complexity and physical limitations increase
Solution Approach 1:
By utilizing the vertical dimension through backside stacking, the patent achieves increased functional density without further reducing horizontal geometry dimensions. This approach bypasses the physical limitations and manufacturing complexity associated with extreme scaling while maintaining high production efficiency.
3Quantity of substance
If passive devices are stacked on the backside of logic devices, then integration density and area utilization are improved, but the manufacturing process complexity increases due to additional processing steps
Solution Approach 1:
The manufacturing process is segmented into front-side processing for logic devices and back-side processing for passive devices. This segmentation allows standard front-end-of-line (FEOL) and mid-end-of-line (MEOL) processes to be completed on the front side, then the substrate is flipped and thinned to enable separate passive device formation on the back side, reducing interference between different device types during manufacturing.
Solution Approach 2:
The patent utilizes the backside of the substrate as an additional manufacturing plane, effectively doubling the available area for device formation. This dimensional transition enables passive devices to be formed in a separate processing stage after substrate thinning, allowing increased integration density while managing process complexity through spatial separation.
Data Source
AI summary
A semiconductor device includes a substrate, a gate all around (GAA) device overlying the substrate, and a thin film transistor (TFT) overlying the GAA device, and a passive device overlying the TFT. The substrate, the GAA device, the TFT, and the passive device is subsequently stacked on each other and at least partially overlap with each other. A via includes a first end, a second end, and a middle portion of the via that is located between the first end and the second end of the via. The first end of the via is connected to the passive device and the second end of the via is connected to one layer of the GAA device. The middle portion of the via is laterally spaced apart from the TFT and the passive device.