3D Logic-Passive Stack With Through-Oxide Vias for Higher Density
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing transistor density due to physical limitations and complexity in manufacturing, particularly in arranging both logic and passive devices on the same substrate, which restricts further miniaturization and integration.
Innovation Solution
A novel integrated logic and passive device structure is proposed, where passive devices are stacked on the backside of logic devices, utilizing a gate-all-around (GAA) MOSFET process with epitaxial SiGe/Si substrates, and through oxide vias (TOVs) connect the front-side logic and backside passive devices, allowing for a high aspect ratio via configuration that enhances integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If logic and passive devices are arranged on the same substrate, then device integration is achieved, but transistor density is limited due to layout restrictions
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional vertical stacking by bonding a first substrate containing logic devices to a second substrate containing passive devices through an interface. This dimensional change allows passive devices to be positioned beneath logic devices, effectively utilizing the vertical dimension to increase transistor density while maintaining device integration.
2Quantity of substance
If geometry size is decreased to increase functional density, then production efficiency improves and costs decrease, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated circuit into separate substrates: a first substrate for logic devices and a second substrate for passive devices. These substrates are manufactured independently at different geometry scales and then bonded together. This segmentation allows each substrate to be optimized separately, reducing manufacturing complexity while achieving high functional density through vertical integration.
3Quantity of substance
If passive devices are stacked on the backside of logic devices, then transistor density increases, but via aspect ratio requirements become more stringent
Solution Approach 1:
The patent introduces an interface layer between the first substrate (logic devices) and the second substrate (passive devices) that facilitates controlled through-substrate via formation. This interface structure acts as a mediator, enabling the creation of vias with manageable aspect ratios by providing a defined pathway through the stacked substrates, thus allowing high transistor density while maintaining manufacturable via dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases transistor density by vertically stacking components, overcoming layout restrictions and physical limitations, thereby improving the integration of semiconductor components within a smaller area.
Implementation Method 1
utilizing a gate-all-around (GAA) MOSFET process with epitaxial SiGe/Si substrates
Data Source
AI summary
A semiconductor device includes a substrate, a gate all around (GAA) device overlying the substrate, and a thin film transistor (TFT) overlying the GAA device, and a passive device overlying the TFT. The substrate, the GAA device, the TFT, and the passive device is subsequently stacked on each other and at least partially overlap with each other. A via includes a first end, a second end, and a middle portion of the via that is located between the first end and the second end of the via. The first end of the via is connected to the passive device and the second end of the via is connected to one layer of the GAA device. The middle portion of the via is laterally spaced apart from the TFT and the passive device.