Logic Circuit Path Verification Using Segmented Timing Constraints
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Solution Overview
Problem
In logic circuit verification, optimizing all paths during functional testing can be resource-intensive and unnecessary, particularly for paths that do not require optimal performance, which reduces test efficiency.
Innovation Solution
A method and system that determine which paths need to achieve optimal performance in the function mode and set a time sequence constraint for those paths to achieve target performance within a specific number of clock cycles, using the ratio of clock frequencies between function and design for test modes, thereby optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all paths are optimized during functional testing to achieve optimal performance, then the reliability and performance of the logic circuit are improved, but the test time and computational resources increase significantly
Solution Approach 1:
The patent segments the set of all paths into two categories: critical paths that require optimal performance and non-critical paths that do not. This segmentation allows the verification process to focus resources only on critical paths, thereby reducing test time while maintaining necessary reliability levels.
Solution Approach 2:
The patent applies different verification strategies to different paths based on their criticality. Critical paths receive full optimization and verification, while non-critical paths use relaxed timing constraints. This local differentiation of quality requirements reduces overall test time without compromising essential circuit performance.
2Reliability
If all paths are optimized during functional testing, then the logic circuit achieves optimal performance, but the computational resources and complexity of the testing process increase
Solution Approach 1:
The verification process is segmented into identifying critical paths and verifying non-critical paths with relaxed constraints. This reduces the complexity of the overall testing process by avoiding unnecessary optimization of non-critical paths while maintaining essential performance requirements.
Solution Approach 2:
Different verification depths and methods are applied locally to different path types. Critical paths undergo comprehensive verification, while non-critical paths use simplified verification with relaxed timing constraints, thereby reducing computational resource requirements and process complexity.
3Productivity
If relaxed timing constraints are applied to non-critical paths, then test efficiency is improved, but the performance of these paths may not meet optimal requirements
Solution Approach 1:
The patent applies relaxed timing constraints specifically to non-critical paths where optimal performance is not essential, while maintaining strict constraints on critical paths. This local quality approach improves test efficiency without compromising the performance requirements of paths that actually need optimal performance.
Solution Approach 2:
Instead of applying full optimization to all paths, the patent applies partial optimization only where necessary. This avoids the excessive action of optimizing non-critical paths, thereby improving test efficiency while maintaining sufficient performance for non-critical functionality.
Data Source
AI summary
A path verification method in a logic circuit includes determining a plurality of first paths that are to be tested in a design for test (DFT) mode, determining a plurality of second paths that are to be tested in a function mode, determining a third path in the plurality of first paths and the plurality of second paths that does not need to achieve optimal performance in the function mode, and setting a time sequence constraint for the third path in the function mode to cause the third path to achieve target performance within a number AA clock cycles. AA is less than or equal to a ratio of a clock frequency in the function mode to a clock frequency in the DFT mode. AA is a positive integer.