Integrated Logic-Physical Verification for IC Yield
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Solution Overview
Problem
Current electronic design automation tools face limitations in their compartmentalized verification flow, which hampers the integration of logical and physical design data, leading to inadequate analysis and optimization of integrated circuit designs, particularly at the 65 nm and below node, where parametric failures dominate yield limitations.
Innovation Solution
An integrated verification platform that performs cross-domain design-dependent verification by combining logical and physical design data, allowing for the selection and analysis of physical design data based on logical components, such as 1-bit SRAM circuits, using a rule-based approach and embedded design data, to enhance the physical analysis and modification of circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional compartmentalized verification flow is used, then verification processes are simpler and more modular, but integration of logical and physical design data is insufficient leading to inadequate analysis
Solution Approach 1:
The patent merges logical design data and physical layout data into a unified verification framework. The system combines netlist information with layout geometry to perform integrated verification, allowing logical components to be directly correlated with their physical representations for comprehensive design validation.
Solution Approach 2:
The verification platform is designed to handle multiple verification tasks across different domains (logical, physical, electrical) through a single integrated system. The same platform performs layout extraction, logical component identification, and design rule checking, providing multi-functional capability that resolves the contradiction between precision and complexity.
2Reliability
If logical and physical design data are integrated, then design analysis and optimization are improved, but verification flow complexity increases
Solution Approach 1:
The patent segments the verification process into distinct but integrated modules: layout extraction, logical component identification, data correlation, and rule-based verification. Each module handles a specific aspect of the verification, allowing complex integrated verification to be managed through organized segmentation of tasks while maintaining high reliability.
Solution Approach 2:
The system introduces an intermediary correlation layer that maps logical components to their physical layout representations. This intermediary structure enables seamless integration of logical and physical data without directly coupling the entire verification system, thereby improving reliability while managing complexity through modular association.
3Productivity
If parametric failures are addressed through integrated verification, then yield is improved, but manufacturing complexity increases
Solution Approach 1:
The verification system performs preliminary identification and analysis of parametric failure risks before manufacturing. By extracting layout data, correlating it with logical components, and applying design rules in advance, the system identifies potential yield issues early in the design phase, allowing corrections before fabrication and improving manufacturing yield without adding complexity to the actual manufacturing process.
Data Source
AI summary
A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data.