Logic Placement Based on Relative Activation Rates
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Solution Overview
Problem
The placement of logic elements in circuit designs, particularly in asynchronous architectures like FPGAs, often results in increased latency and reduced throughput due to the need for additional buffering, which is exacerbated by longer signal paths and cyclically activated handshake signals.
Innovation Solution
Determining the relative activation rates of control paths in high-level language programs and using these rates to guide the placement of logic functions on integrated circuit devices, minimizing placement costs and optimizing signal connections to reduce latency and improve throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If logic elements are placed using conventional placement algorithms, then placement coverage is achieved, but latency increases and throughput decreases due to longer signal paths requiring additional buffers
Solution Approach 1:
The patent applies local quality by differentiating placement strategies based on signal activation rates. High-activation-rate signals receive prioritized placement attention to minimize their path lengths and buffer requirements, while low-activation-rate signals are placed with standard constraints. This localized optimization resolves the contradiction by improving latency for critical signals without compromising overall placement coverage.
Solution Approach 2:
The patent changes the placement cost function parameters to include signal activation rates. By weighting placement costs according to activation rates, the algorithm dynamically adjusts placement decisions to minimize latency for frequently activated signals. This parameter change enables the system to reduce latency for critical paths while maintaining acceptable throughput for the overall circuit.
2Reliability
If additional buffers are inserted to achieve timing closure in synchronous design or limit skew in asynchronous design, then timing requirements are met, but device complexity increases and performance deteriorates
Solution Approach 1:
The patent applies preliminary action by determining signal activation rates during the compilation phase, before physical placement. This early identification of high-activation-rate signals allows the placement algorithm to proactively position logic elements to minimize buffer requirements, rather than reactively adding buffers after placement. This preliminary analysis reduces the total number of buffers needed while ensuring timing closure.
Solution Approach 2:
The patent enables the placement algorithm to self-optimize by using activation rate information to automatically adjust placement costs. The system serves itself by identifying which signals need optimization and automatically configuring placement parameters to minimize buffer insertion, reducing device complexity while maintaining reliability.
3Area of stationary object
If logic functions are placed to minimize overall placement cost, then area utilization is optimized, but high-activation-rate signal paths may suffer from increased latency due to longer routes
Solution Approach 1:
The patent applies local quality by creating differentiated placement cost weights for different signal types. High-activation-rate signals are assigned higher weights in the placement cost function, causing the algorithm to prioritize their placement quality over global area utilization. This local optimization resolves the contradiction by accepting slightly reduced area efficiency to achieve significant latency reduction for critical signals.
Solution Approach 2:
The patent changes the placement cost function to include activation-rate-based weighting parameters. By modifying the cost parameters to reflect signal importance, the algorithm balances area utilization and latency differently for different signals. This parameter change enables simultaneous optimization of both area and latency by allowing the system to trade off area efficiency for latency reduction in critical paths.
Data Source
AI summary
Approaches for placing logic of a circuit design include determining respective relative activation rates of control paths in a high-level language (HLL) program by a design tool. The HLL program specifies a circuit design. The design tool compiles the HLL program into logic functions and determines respective relative activation rates of signal connections between the logic functions based on the relative activation rates of the control paths in the HLL program. The design tool selects placement locations on an integrated circuit device for the logic functions using a placement cost minimization function that factors the relative activation rates of the signal connections into placement costs.