Logic and Power Device Fabrication on Shared Substrate
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Solution Overview
Problem
As device dimensions decrease, forming individual components and electrical contacts for Field Effect Transistors (FETs) becomes increasingly difficult, necessitating a method that retains the advantages of traditional FET structures while overcoming scaling issues.
Innovation Solution
The method involves forming a logic device and a power device on the same substrate using a set of vertical fins, with an isolation region separating the regions, and employing a thick dielectric under-layer and an inverted T-shaped gate structure to differentiate and enhance the voltage/current capacity of power devices, allowing for simultaneous fabrication of high voltage/power and low voltage/power devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are decreased to improve integration density, then productivity and integration density improve, but manufacturing precision and ease of forming individual components deteriorate
Solution Approach 1:
The substrate is divided into first and second regions with different device types (logic and power devices) separated by an isolation region. This segmentation allows each region to be optimized independently for its specific device requirements while maintaining overall integration on the same substrate, resolving the contradiction between high integration density and manufacturing precision for different device types.
Solution Approach 2:
Different structures are applied to different regions: the first region uses structures optimized for logic devices while the second region uses structures optimized for power devices. This local differentiation allows each region to achieve optimal manufacturing precision for its specific device type while maintaining high overall integration density through shared substrate utilization.
2Ease of manufacture
If traditional FET structures are used to maintain ease of manufacture, then ease of manufacture is preserved, but voltage/current handling capability for power devices deteriorates
Solution Approach 1:
The patent applies different structural configurations to different regions: logic devices in the first region use conventional structures for ease of manufacture, while power devices in the second region use specialized structures (such as thicker dielectric layers, modified gate structures) to enhance voltage and current handling capability. This local differentiation resolves the contradiction by allowing each region to be optimized for its primary requirement.
Solution Approach 2:
By segmenting the substrate into distinct logic and power device regions, the patent enables power devices to have enhanced structures specifically where needed without compromising the ease of manufacture for logic devices. The isolation region physically separates these requirements, allowing each to be optimized independently.
3Reliability
If separate substrates are used for logic and power devices to optimize each device type, then voltage/current handling capability and device optimization improve, but device complexity and fabrication processes deteriorate
Solution Approach 1:
The patent merges logic devices and power devices onto a single substrate, sharing common fabrication processes, substrate preparation, and base structures. This combination reduces overall device complexity and simplifies fabrication processes compared to using separate substrates, while still allowing each device type to be optimized for its specific requirements through regional differentiation and isolation.
Data Source
AI summary
A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.